SC1480A Datasheet, PDF (17/23 Pages) Semtech Corporation – DDR and DDR Memory VTT power Supply Controller

POWER MANAGEMENT
Application Information (Cont.)
SC1480A
.igure 8: Power Section Component Placement and Copper Pours
Key points for the power section:
1) there should be a very small input loop, well decoupled.
2) the phase node should be a large copper pour, but compact since this is the noisiest node.
3) input power ground and output power ground should not connect directly, but through the ground planes instead.
4) Notice in .igure 8 above placement of 0Ω resistor at the bottom of the output capacitor to connect to VSSA.
5) The current limit resistor should be placed as close as possible to the ILIM and LX pins.
Connecting the control and power sections should be accomplished as follows (see .igure 9 on Page 18):
1) Route VSSA and .B feedback traces as a differential pair routed in a “quiet” layer away from noise sources.
2) Route DL, DH and LX (low side .ET gate drive, high side .ET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high
frequencies, thus should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the
ground plane.
 2003 Semtech Corp.
17
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