SC120 Datasheet, PDF (16/21 Pages) Semtech Corporation – Low Voltage Synchronous Boost Converter

SC120
Applications Information (continued)
The Enable Pin
Note that startup with a regulated active load is not the
The EN pin is a high impedance logical input that can be same as startup with a resistive load. The resistive load
used to enable or disable the SC120 under processor output current increases proportionately as the output
control. V < 0.2V will disable regulation, set the LX pin in
EN
voltage rises until it reaches programmed V /R , while
OUT LOAD
a high-impedance state (turn off both FET switches), and a regulated active load presents a constant load as the
turn on an active discharge device to discharge the output
capacitor via the OUT pin. V > 0.85V will enable the
EN
output. The startup sequence from the EN pin is identical
to the startup sequence from the application of input
output voltage rises from 0V to programmed V . Note
OUT
also that if the load applied to the output exceeds an
applicable V –dependent startup current limit or duty
OUT
cycle limit, the criterion to advance to the next startup
power.
stage may not be achieved. In this situation startup may
pause at a reduced output voltage until the load is reduced
Regulator Startup, Short Circuit Protection, and
Current Limits
L ^{The SC120 permits power up at input voltages from 0.85V}
to 3.8V. Startup current limiting of the internal switching
IA ^{n-channel and p-channel FET power devices protects}
them from damage in the event of a short between OUT
and GND. As the output voltage rises, progressively less-
T _{restrictive current limits are applied. This protection}
unavoidably prevents startup into an excessive load.
EN To begin, the p-channel FET between the LX and OUT pins
turns on with its current limited to approximately 150mA,
ID ^{the short-circuit output current. When V approaches V}
OUT
IN
(but is still below 1.7V), the n-channel current limit is set
F ^{to 350mA (the p-channel limit is disabled), the internal}
oscillator turns on (approximately 200kHz), and a fixed
N ^{75% duty cycle PWM operation begins. (See the section}
PWM Operation.) When the output voltage exceeds 1.7V,
O ^{normal fixed frequency variable duty cycle PWM opera-}
C ^{tion begins, with the n-channel FET’s current limited to}
further.
Output Overload and Recovery
When in PSAVE operation, an increasing load will eventu-
ally satisfy one of the PSAVE exit criteria and regulation
will revert to PWM operation. As previously noted, the
PWM steady state duty cycle is determined by
D = 1 – (V /V ), but must be somewhat greater in prac-
IN OUT
tice to overcome dissipative losses. As the output load
increases, the dissipative losses also increase. The PWM
controller must increase the duty cycle to compensate.
Eventually, one of two overload conditions will occur,
determined by V , V , and the overall dissipative losses
IN OUT
due to the output load current. Either the maximum duty
cycle of 90% will be reached or the n-channel FET 1.2A
(nominal) peak current limit will be reached, which effec-
tively limits the duty cycle to a lower value. Above that
load, the output voltage will decrease rapidly and in
reverse order the startup current limits will be invoked as
the output voltage falls through its various voltage thresh-
350mA to prevent excessive output voltage overshoot. If olds. How far the output voltage drops depends on the
the n-channel FET current limit is exceeded, the on-state load V-I characteristics.
ends immediately and the off-state begins, overriding the
output voltage regulation controller. This reduces the ^{A reduction in input voltage, such as due to a discharging}
duty cycle on a cycle-by-cycle basis. When V is within battery, will lower the load current at which overload
OUT
2% of the programmed regulation voltage, the n-channel ^{occurs. Lower input voltage increases the duty cycle}
FET current limit is raised to 1.2A.
required to produce a given output voltage. And lower
input voltage also increases the input current to maintain
Once variable duty cycle PWM operation is initiated, the the input power, which increases dissipative losses and
output becomes independent of V and output regula-
IN
tion can be maintained for V as low as 0.7V, subject to the
IN
maximum duty cycle and peak current limits. The duty
further increases the required duty cycle. Therefore an
increase in load current or a decrease in input voltage can
result in output overload.
cycle must remain between 15% and 90% for the device
to operate within specification.
Once an overload has occurred, the load must be
decreased to permit recovery. The conditions required for
PRELIMINARY
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