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SC4524B_08 Datasheet, PDF (14/18 Pages) Semtech Corporation – 18V 2A Step-Down Switching Regulator
C5
=
2
π
⋅

6
⋅

0

3
⋅
2
2
.
⋅

0
3
= 0.45nF
C8
=
2
π⋅
6
00
⋅

0 3
⋅ 22. ⋅0 3
= 2pF
SC4524B
Applications Information (Cont.)
(230)%PloafcVVteoche=thc(eroc+sossom/vpGeωerPpnWf)rMs(ea(qt+ou+res ns/zRceωyrEno,SQRF, CCF+.OZ1s),2b/eωtwn2 )een 10% and
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
(4) Use the compensator pole, FP1, to cancel the ESR zero, operation, the size of the loop formed by these components
FZ.
(5)
TheGnP,WtMhe≈
pGaCrARa⋅mR Set, ers
can be calculated by
of
theωpco≈mRpCeOn,sation
neωtwZo=rkR ESRCsitnhhOteoe, ugfrlredaetbweedhemweiiltnihnimignidztheioded.SeSCicn4loc5e2se4tBhto,ectpohonewnneeecrgtisanwtgiivttechhteeirsamnaoilnrdeaealdooyff
AC
R7
= 0 20
gm
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
C5
=

2 πFZ
R7
C8
=

2 πFP
R7
where gm=0.28mA/V is the EA gain of the SC4524B.
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
Example: Determine the voltage compensator for an avoid using vias directly under the device.
800kHz, 12V to 3.3V/2A converter with 22uF ceramic
output capacitor.
V IN
Choose a loop gain crossover frequency of 80kHz, and
p(r2elA0aqCc%u=eir−evoA2dof0Clct⋅F=laooCggm)−,eGp2aCce0AnoRnd⋅mSslao⋅pF2tgoePπ1Frn=GCgsC6aCaO0AtiRo0⋅nVkVrSFaOHBzt⋅zeF2.rCoπFiFsraConCmdO p⋅EoVqVlFuOeBaatitonFZ1(=91),6ktHhez
VOUT
AC
=
−A2 0C
⋅=log−

20
28 ⋅
6⋅.lo⋅g0
2−38⋅
2⋅
π6⋅.

80⋅⋅00 3−⋅32
⋅
2
2⋅ π0
−⋅68⋅03..⋅030=3
5 . 9 dB
⋅ 22
⋅

0
−6
⋅
.0
3.3

=
5
.9
dB
ZL
Then the c5o.9 mpensator parameters are
R7
C5
=
=
0
0 20
.28 ⋅0 −3
R7 = 0.
= 22.53.9k
0 20
28 ⋅ 0
−3
2π ⋅6 ⋅0 3 ⋅ 22. ⋅0 3
=
=
22.3k
0 . 4 5 nF
C8
=
C5
2 π⋅ 6
=
00

2⋅π0 3⋅
⋅ 262

.⋅⋅0 03 3
⋅
=222.pF
⋅

0
3
= 0.45nF
Vo
Vc
=
C8
( + s
=GP2WMπ(⋅ 6+0sR0ES⋅RC0O)3
/ ωp )( + s / ωn Q + s 2
⋅ 22.
/ ωn2 )
⋅0
3
= 2pF
Select R7=22.1k, C5=0.47nF, and C8=10pF for the design.
Figure 9. Heavy lines indicate the critical pulse
current loop. The inductance of this
loop should be minimized.
CarGoePmWlMips≈teeVVGndocCsAR=ai⋅nRto(STr,a+bplaser/a4Gmω. APωpeWp)tMM(e≈(raRs+tCh+fOsoC,s/rARωvDEanSrQRpioCr+ouOωgss)Z2rt=ay/RmpωEiScRin2sCa)Oal ,laspopalivcaaitlaiobnles
AC
upPRpaCC7r5oBa==nmL2rag0GeeπmytF2qP0eoZWuruMRset.7s≈Ct foGonCrAsRdi⋅deRteSari,aletdiocnaslculωatpio≈nRoCf
the
,
O
compensator
ωZ = R
E

SR
C
O
,
C
In
8=
a

AC
s2tRπeF7pP=-Rd7og0wm2n0
switching
regulator,
the
input
bypass
C5
=
2 πF
R
Vin
Cu
+
14