TS51111 Datasheet, PDF (12/22 Pages) List of Unclassifed Manufacturers – High Efficiency Synchronous Rectifier and Charging IC for Wireless Power Applications

F^USu^Bnctional Description (continued)
The TS51111 will automatically detect the presence of a
voltage applied to the USB pin. If the USBCTRL bit is set low
and a voltage is applied to the USB pin, the part will respond
by disabling all charging paths to the battery and switching
the LDO power input from the battery to the USB. If the
USBCTRL bit is set hi, the part will not automatically disable
charging or switch the LDO power input. The USBCTRL
bit is programmed in Non-Volatile Memory (NVM) during
manufacturing and is not user configurable. In either
condition, the USBDET bit in the FAULT register will be set.
When USB power is removed, the part will return to normal
operation.
LDO
The TS51111 LDO supports a variety of system configurations.
An on-chip ultra-low Iq LDO is provided for powering
external system components when a battery or USB supply is
available. The LDO is designed to operating with minimum
quiescent but can still deliver high output current at low
dropout voltage. Integrated current limit provides additional
protection.
If an external USB power supply is available, the LDO will draw
its input power from the USB pin instead of from the battery.
In the event that neither an external USB supply nor an
external battery is available, the LDO will automatically power-
up of the rectified voltage when incoming power is detected
and provide power to an external microcontroller.
To support multiple possible external microcontrollers, the
internal LDO has a configurable output voltage. The voltage
is set according to the following table. The LDOSET<1:0>
bits are programmed in Non-Volatile Memory (NVM) during
manufacturing and are not user configurable.
LDOSET<1:0>
00
01
10
11
VCORE (V)
1.5
1.8
2.5
3.3 (default)
VAC Detect
The presence of incoming power on the coils will be indicated
by the TS51111 by asserting the VAC_DET output pin. The pin
will be de-asserted when incoming power is removed. The
VAC_DETECT output can be configured as open-drain with an
external resistor pull-up or as a totem pole with a VCORE high
level. This is set using the VAC_CNFG bit with hi for open-drain
and low for totem-pole.
UART
UART level translators are included to facilitate communication
between system components. The level shifters will translate
voltage levels from VCORE for the system microprocessor to
PACKP for a separate system.
VREF
An internal high-accuracy VREF circuit provides a precision
reference for external analog-to-digital converters. Integrated
voltage dividers provide sense voltages for external ADC
measurement. The VREF circuit is enabled using the EN_VREF
bit and will not draw any current when not active.
OVP
An on-board over-voltage sensor on the PDC signal is available
if additional external over-voltage protection is needed. In an
over-voltage condition, the OVP FET is active to provide a low
impedance path to ground on the OVP pin. In addition, the
OVP FET can be forced on using the register bit. This can be
used to provide an additional load on PDC if required. In an
OVP condition, the OVP bit of the FAULT register will be set hi.
Temperature Sensing
The die temperature of the TS51111 is measured using an
onboard temperature sensor. The output of the temperature
sensor is available on the AMUX pin.
If the temperature of the TS51111 exceeds the TSD threshold,
all high current operations will be disabled until the die
temperature reaches a safe level. Temperature hysteresis
prevents rapid entering and exiting of the over-temperature
state. In thermal shutdown, the load switch, precharge
current, and synchronous rectifier are disabled. All other
functions including OVP and MOD will still be available. When
the TSD threshold is hit, the TSD bit in the FAULT register will
be set.
TS51111
Final Datasheet
April 17, 2015
Rev 2.2
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