SC2442 Datasheet, PDF (1/10 Pages) Semtech Corporation – High Performance Wide Input Range Dual Synchronous Buck Controller

SC2442/H
High Performance Wide Input Range
Dual Synchronous Buck Controller
POWER MANAGEMENT
Description
SC2442 and SC2442H are high performance dual buck
converter controllers that can be configured for a variety
of synchronous buck applications where efficiency is most
important. Both converters are synchronized to prevent
beat frequencies. The dual buck converters are also
operated out of phase reducing input ripple, allowing for
fewer input capacitors.
High frequency operation up to 1.1 MHz reduces the size
of output inductors and capacitors. The controller has
separate power pins for both VCC and GND to improve
noise immunity. The VCC supplies can be regulated to 7V
using an external PNP transistor. Other features include:
bootstrapping for high side drive supplies, asynchronous
mode start up, power up sequencing to prevent latch-
ups, individual soft start for each convertor, bootstrapped
drivers for high side N-channel MOSFETs, input side
current sensing, dual mode current limit with hiccup,
enable and external frequency synchronization.
The SC2442 operates over the range of 4.75V to 30V
and SC2442H operates over the range of 4.75V to 36V.
Typical Application Circuit
Features
‹ Dual output controller
‹ Asynchronous start up mode
‹ Power up sequencing to prevent latch-ups
‹ Out of phase operation for low input ripple
‹ Over current protection
‹ Output down to 0.75V
‹ Wide input range, 4.75 to 30V for SC2442 and
4.75 to 36V for SC2442H
‹ Vcc regulator with external PNP transistor
‹ Programmable clock frequency up to 1.1MHz
‹ Two synchronous bucks for high efficiency at high
current
‹ –40 to +125 Deg C operating temperature
‹ Small package TSSOP-24
‹ Fully WEEE and RoHS Compliant
Applications
‹ Point of load converter applications
‹ DSL applications with multiple output voltages
‹ Power management for mixed signal applications
‹ Cable modems and set top boxes.
VIN+ ^{MAX 30V/36V (H)}
R1
R2
C1
Q5
C6
R9
C7
RTN
R3
R4
OC1
OC2
C4
C5
C8
C9
R1 2
RTN
R10
SS1
SS2
OSC
AVCC
PVCC
3 _VIN
2 _BDI
U1 ^{OC1 4}
OC 2 ²¹
1 _AVCC
GD1H ⁹
13 _{P VC C}
G D 1L ¹¹
7 _SS1
G D 2H ¹⁶
18 _{S S 2}
G D 2L ¹⁴
23 _{ROS C}
P H 1 ¹⁰
6 _FB1
BST1 ⁸
5 _{E A1}
P H 2 ¹⁵
19 _FB2
BS T 2 ¹⁷
20 _{E A2}
P G ND ¹²
22 _{S YN C /E N AG ND} 24
Q1
R5
Q3
R7
Q2
D1 D2
R6
Q4
R8
PH1
BST1
PH2
BST2
C15
C1 6
L1
C2
VOUT1
RTN
L2
VOUT2
C3
RTN
R13
R1 4
R15
R1 6
R11
C10
C1 1
EA2
RTN
R17
C1 2
R18
C13
FB2
ENA
FB1
Revision: June, 2007
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