2N7002CSM Datasheet, PDF (1/2 Pages) Seme LAB – N-CHANNEL ENHANCEMENT MODE MOS TRANSISTOR

2N7002CSM
MECHANICAL DATA
Dimensions in mm (inches)
0.51 ± 0.10
(0.02 ± 0.004)
3
0.31
(0.012)
rad.
2
1
1.91 ± 0.10
(0.075 ± 0.004)
3.05 ± 0.13
(0.12 ± 0.005)
0.31
(0.012)
rad.
A = ^{1.02 ± 0.10}
(0.04 ± 0.004)
A
1.40
(0.055)
max.
SOT23 CERAMIC
(LCC1 PACKAGE)
Underside View
PAD 1 – Gate PAD 2 – Source PAD 3 – Drain
N–CHANNEL
ENHANCEMENT MODE
MOS TRANSISTOR
FEATURES
• V_(BR)DSS = 60V
• RDS_(ON) = 7.5Ω
• I_D = 0.115A
ABSOLUTE MAXIMUM RATINGS (T_CASE = 25°C unless otherwise stated)
V_DS
Drain – Source Voltage
60V
V_GS
Gate – Source Voltage
±40V
I_D
Drain Current
@ T_CASE = 25°C
±0.115A
I_D
Drain Current
@ T_CASE = 100°C
±0.073A
I_DM
Pulsed Drain Current *
0.8A
P_D
Power Dissipation
@ T_CASE = 25°C
200mW
P_D
Power Dissipation
@ T_CASE = 100°C
80mW
T_j
Operating Junction Temperature Range
–55 to 150°C
T_stg
Storage Temperature Range
–55 to 150°C
* Pulse width limited by maximum junction temperature.
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Prelim. 7/98