SS2015 Datasheet, PDF(1/6 Page) SEC Electronics Inc. – CMOS High Sensitivity Micropower Hall Latch

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SS2015 Datasheet, PDF (1/6 Pages) SEC Electronics Inc. – CMOS High Sensitivity Micropower Hall Latch

Packages

SS2015

CMOS High Sensitivity Micropower Hall Latch

3 pin SIP (suffix UA)

Features and Benefits

1. Operation down to 4.5V

2. Wide operating voltage range

3. High sensitivity for direct reed switch re-

placement applications

4. Output switches with absolute

value of North or South pole from magnet

5. Temperature compensation

6. Open-Collector pre-driver

7. 60V maximum withstand voltage

8. Reverse polarity protection

9. Package: TO-92S(SIP)

Functional Block Diagram

Application Examples

1. Brush-less DC Motor

2. Brush-less DC Fan

3. Revolution counting

4. Speed measurement

General Description:

The SS2015 Hall effect latch sensor IC is fabricated from mixed signal CMOS technology. It incorporates ad-

vanced chopper-stabilization techniques to provide accurate and stable magnetic switch points.

The circuit design provides an internally controlled clocking mechanism to cycle power to the Hall element and

analog signal processing circuits. This serves to place the high current-consuming portions of the circuit into a

âSleepâ mode. Periodically the device is âAwakenedâ by this internal logic and the magnetic flux from the Hall

element is evaluated against the predefined thresholds. If the flux density is above or below the BOP/BRP thresh-

olds then the output transistor is driven to change states accordingly. While in the âSleepâ cycle the output tran-

sistor is latched in its previous state. The design has been optimized for service in applications requiring extended

operating lifetime in battery powered systems. An internal bandgap regulator is used to provide temperature com-

pensated supply voltage for internal circuits and allows a wide operating supply range.

The output transistor of the SS2015 will be latched on (BOP) in the presence of a sufficiently strong South or

North magnetic field facing the marked side of the package. The output will be latched off (BRP) in the absence

of a magnetic field.

V3.10 Nov 1, 2013

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