LE25S40MB Datasheet, PDF (9/22 Pages) Sanyo Semicon Device – 4M-bit (512K×8) Serial Flash Memory

LE25S40MB
BP0, BP1, BP2, TB (Bits 2, 3, 4, 5)
Block protect BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected
can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting conditions".
BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order
address area or lower-order address area.
Table 5 Protect Level Setting Conditions
Protect Level
Status Register Bits
TB
BP2
BP1
BP0
0 (Whole area unprotected)
X
0
0
0
T1 (Upper side 1/8 protected)
0
0
0
1
T2 (Upper side 1/4 protected)
0
0
1
0
T3 (Upper side 1/2 protected)
0
0
1
1
B1 (Lower side 1/8 protected)
1
1
0
1
B2 (Lower side 1/4 protected)
1
1
1
0
B3 (Lower side 1/2 protected)
1
1
1
1
4 (Whole area protected)
X
1
X
X
* Chip erase is enabled only when the protect level is 0.
Protected Area
None
07FFFFh to 070000h
07FFFFh to 060000h
07FFFFh to 040000h
00FFFFh to 000000h
01FFFFh to 000000h
03FFFFh to 000000h
07FFFFh to 000000h
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers
are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP setting
conditions".
Table 6 SRWP Setting Conditions
WP _Pin
0
1
SRWP
0
1
0
1
Status Register Protect State
Unprotected
Protected
Unprotected
Unprotected
Bit 6 are reserved bits, and have no significance.
3. Write Enable
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is
the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.
"Figure 7 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable
command consists only of the first bus cycle, and it is initiated by inputting (06h).
• Small sector erase, sector erase, chip erase
• Page program
• Status register write
No.A2096-9/22