LC74950BG Datasheet, PDF (9/37 Pages) Sanyo Semicon Device – CMOS IC Silicon gate 40/30MSPS Analog Display I/F LSI

Pin Connection
1) ADC and its peripherals
VRTx VRBx
0.1μF
LC74950BG
VRTx: VRT0, VRT1, VRT2
VRBx: VRB0, VRB1, VRB2
10μF 0.1μF 0.1μF
10μF
0.1μF
Terminal
resistor
xINx
YGIN0, YGIN1
CRIN0, CRIN1
CBIN0, CBIN1
2) PLL and its pereipherals
CHRGPMP
3.3kΩ
0.068μF
0.0039μF
3) Output pin (recommended)
CBOUT0-3
5pF
4) Power supplies
The analog A** and digital D** power supplies must be supplied separately without fail. In addition, the power
supply for the PLL circuit must also be provided separately as it will affect the jitter characteristics of the PLL circuit.
For ADC power supply, it is desirable to provide separate power for eachof the ADC channel.
AVDD33_PLL : Must be separated by L components, etc.
ADC2AVDD33A : Separating by L components, etc. recommended
ADC1AVDD33A : Separating by L components, etc. recommended
ADC0AVDD33A : Separating by L components, etc. recommended
5) Unused pin treatment
YGIN0, 1/CBIN0, 1/CRIN0, 1: Open
PDWN: Pull up
CHRGPMP: Open (when PLL is not in use)
***OUT* (e.g., YGOUT0): Open
HSIN/VSIN: Must always be configured for input.
RESET: Must always be configured for input.
COAST: Must be connected to DVSS.
TEST, SCANEN, SCANMOD: DVSS
CLKIN: DVSS
HSOUT, VSOUT, DEOUT: Open
SVO, ATB: Open
* The specified voltage of power must be applied to each of the power supply pin even if it is not to be used
(PLL is not to be used, for example).
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