LC72147V Datasheet, PDF (9/22 Pages) Sanyo Semicon Device – PLL Frequency Synthesizer for Electronic Tuning in Car Audio Systems

LC72147V
DI control data description
No.
Control block/data
Content
• This data sets the divisor for the programmable divider
P0 is the LSB, and P15 is the MSB of this binary value.
Programmable divider data
DVS = 0: The FMIN pin is pulled down.
(1)
P0 to P15
1: Selects the FMIN pin.
DVS
Divisor setting (N): 272 to 65,536
Input frequency range: 10 to 180 MHz
*: See the “Programmable Divider Structure” item for details.
Related data
• This data controls the sub-charge pump.
PDC1 PDC0
Sub-charge pump state
(* : don’t care)
0
*
High impedance
Sub-charge pump control data
(2)
PDC0, PDC1
1
0 Charge pump operating (PLL unlocked)
1
1 Charge pump operating (normal operation)
UL0, UL1, DLC
*: The sub-charge pump output is connected internally to the gate of the transistor used for
low-pass filter formation. The sub-charge pump can be used in conjunction with the PD
pin (main charge pump pin) to form a high-speed locking circuit.
See the “Charge Pump Structure” item for details.
• Reference frequency selection data
R3
R2
R1
R0
Reference frequency (kHz)
0
0
0
0
100 *¹
0
0
0
1
50
0
0
1
0
25
0
0
1
1
25
0
1
0
0
12.5
0
1
0
1
6.25
0
1
1
0
3.125
0
1
1
1
3.125
Reference divider data
(3)
R0 to R3
1
0
0
0
1
0
0
1
1
0
1
0
10
9 *²
5
1
0
1
1
1
1
1
0
0
3 *²
1
1
0
1
30 *²
1
1
1
0 *³ PLL inhibit + X’tal OSC stop
1
1
1
1 *³ PLL inhibit
Notes: 1. Illegal value when a crystal oscillator frequency of 10.25 or 10.35 MHz is selected.
2. Illegal value when a crystal oscillator frequency of 10.25 MHz is selected.
3. PLL inhibit (backup mode)
The programmable divider block is stopped, the FMIN pin is pulled down to ground, and
the charge pump output is set to the floating state.
Continued on next page.
No. 6675-9/22