LV51140T Datasheet, PDF (8/13 Pages) Sanyo Semicon Device – CMOS IC 1-Cell Lithium-Ion Battery Protection IC

LV51140T
Description of Operation
• Normal condition
This IC monitors the battery voltage (VDD) and the voltage of VM terminal, and controls charge and discharge.
If the battery voltage (VDD) is in the range from the over-discharge detection voltage (Vdc) to the over-charge detection
voltage (VC) and the VM terminal voltage is in the range from the charge over-current detection voltage (VIc) to the
discharge over-current detection voltage (VIdc), this IC turns on both the charge and discharge control FETs. This state
is called the normal condition, and charge and discharge are possible together.
• Discharge over-current detection, Load short-circuiting detection
When the discharge current becomes equal to or higher than the specified value under the normal condition, and if the
VM terminal voltage is in the range from the discharge over current detection voltage (VIdc) to the short-circuiting
detection voltage (Vshort) and that state is maintained during more than the discharge over-current detection delay time
(tidc), this IC turns off the discharge control FET to stop discharge. This state is called the discharge over-current
condition.
At that time, if the VM terminal voltage is equal to or higher than Vshort and that state is maintained during more than
the load short-circuiting detection delay time (tshort), this IC turns off the discharge control FET to stop discharge. This
state is called the load short-circuiting detection condition.
While load is connected, in both conditions, the VM terminal voltage equals to VDD potential due to the load, but it falls
by the discharge over-current release resistance (Rdwn) when the load is removed and the resistance between (+) and (-)
terminals of battery pack (refer to “Application Circuit Example”) becomes larger than the value which enables the
automatic return.
Then the VM terminal voltage becomes less than VIdc, and if that state is maintained during more than the release delay
time 1 (trel1), this IC returns to normal condition.
Note : The resistance value between (+) and (-) terminals of battery pack for automatic return changes with battery voltage
(VDD) or VIdc. The standard is expressed with the following equation.
Resistance value for automatic return = Rdwn × (VDD / VIdc - 1)
• Charge over-current detection
When the charge current becomes equal to or higher than the specified value under the normal condition, if the VM
terminal voltage becomes less than the charge over-current detection voltage (VIc) and that state is maintained during
more than the charge over-current detection delay time (tic), this IC turns off the charge control FET to stop charge. This
state is called the charge over-current detection condition.
Then the VM terminal voltage becomes equals to or higher than VIc and that state is maintained during more than the
release delay time 1 (trel1) when the charger is removed and the load is connected, this IC returns to the normal
condition.
Note : If the VM terminal voltage becomes equal to or less than VSS-7V (typical), the charge over-current detection delay
time (tic) changes as below.
8ms model → 8ms (not changed)
125ms model → 7ms (typical)
1.0s model → 56ms (typical)
• Over-charge detection
When the battery voltage (VDD) under the normal condition becomes equal to or higher than the over-charge detection
voltage (VC) and that state is maintained during more than the over-charge detection delay time (tc), this IC turns off the
charge control FET and stops charge. This state is called the over-charge detection condition. Release from the
over-charge detection condition includes following three cases.
(1) When VDD falls to Vc-VHc without load and that state is maintained during more than the delay time 2 (trel2), this
IC turns on the charge control FET and returns to the normal condition.
* VHc : Over-charge hysteresis voltage
(2) When the load is installed and discharge starts, the discharge current flows through the internal parasitic diode of the
charge control FET. Then the VM terminal voltage rises to only the Vf voltage of the internal parasitic diode from
VSS potential. At this time, if the VM terminal voltage is higher than the discharge over-current detection voltage
(VIdc) and VDD is equal to or less than VC, this IC returns to the normal condition when this state continues more
than the delay time 2 (trel2).
(3) In case (2), if the VM terminal voltage is higher than the discharge over-current detection voltage (VIdc) and VDD
is equal to or higher than VC, battery is discharged until VDD becomes less than VC, and then this IC returns to the
normal condition when this state continues more than the delay time 2 (trel2).
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