LE24CB1283 Datasheet, PDF (8/12 Pages) Sanyo Semicon Device – Two Wire Serial Interface EEPROM (128K EEPROM)

LE24CB1283
6 EEPROM write operation
6-1. Byte writes
The write operation requires a 7-bit device address word with the 8^th bit = 0(write). Then the EEPROM sends
acknowledgement 0 at the 9^th clock cycle. After these, the EEPROM receives word address (A15 to A8), and the
EEPROM outputs acknowledgement 0. And then, the EEPROM receives word address (A7 to A0), and the EEPROM
outputs acknowledgement 0. Then the EEPROM receives 8-bit write data, the EEPROM outputs acknowledgement 0
after receipt of write data. If the EEPROM receives a stop condition, the EEPROM enters an internally timed (tWC)
write cycle and terminates receipt of inputs until completion of the write cycle.
SDA
Word Address
Data
1 0 1 0 S2 S1 S0 W
A
15
A
14
A
13
A
12
A
11
A
10
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
ACK
ACK
R/W
Access from master
6-2. Page writes
The Page write allows up to 64 bytes to be written in a single write cycle. The page write is the same sequence as the
byte writes except for inputting the more write data. The page write is initiated by a start condition, device code,
device address, memory address (n) and write data (n) with every 9^th bit acknowledgement. The device enters the
page write operation if this device receives more write data (n+1) instead of receiving a stop condition. The page
address (A0 to A5) bits are automatically incremented on receiving write data (n+1). The device can continue to
receive write data up to 64 bytes. If the page address bits reach the last address of the page, the page address bits will
roll over to the first address of the same page and previous write data will be overwritten. After these, if the device
receives a stop condition, the device enters an internally timed (tWC × (n+x)) write cycle and terminates receipt of
inputs until completion of the write cycle.
SDA
1 0 1 0 S2 S1 S0 W
A
15
A
14
A
13
A
12
A
11
A
10
A9 A8
ACK
R/W
Word Address(n)
A7 A6 A5 A4 A3 A2 A1 A0
ACK
Data(n)
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
Data(n+1)
Data(n+x)
D7 D6 D1 D0
D7 D6 D1 D0
ACK
ACK
D7 D6 D1 D0 D7 D6 D1 D0
ACK
ACK
Access from master
6-3. Acknowledge polling
The Acknowledge polling operation is used to show if the EEPROM is in an internally timed write cycle or not. This
operation is initiated by the stop condition after inputting write data. This requires the 8-bit device address word with
the 8^th bit = 0 (write) following the start condition during an internally timed write cycle. If the EEPROM is busy
with the internal write cycle, no acknowledge will be returned. If the EEPROM has terminated the internal write
cycle, it responds with an acknowledge. The terminated write cycle of the EEPROM can be known by this operation.
During Write
During Write
End of Write
SDA
1 0 1 0 S2 S1 S0 W
1 0 1 0 S2 S1 S0 W
1 0 1 0 S2 S1 S0 W
NO ACK
R/W
NO ACK
R/W
ACK
R/W
Access from master
No.1887-8/12