LC07424LP Datasheet, PDF (8/32 Pages) Sanyo Semicon Device – CMOS IC Audio CODEC with Video Driver

LC07424LP
Analog Characteristics at Ta=25±2°C, VDDh=VDDvh=4.8V, VDDana=VDDsp=VDDv=2.8V, VDDio=VDDdig=1.8V,
VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V, 0dBFS=-3.9dBV=1.8V
Unless otherwise specified, fs=48kHz, signal frequency =1kHz (sin wave), measurement range=20Hz to 20kHzDAC_DIN pin input=0dBFS
PGA gain setting=0dB, EVR gain setting=0dB
Analog Input / output
Parameter
Input voltage
Input impedance
Total harmonic distortion ratio
and noise
ADC analog Input
Resolution
SNR
Symbol
LI_VIN
LI_RIN
AA_THD+N
ADC_RES
ADC_SNR
Conditions
(*1)
(*1) (*2)
LIN_L pin input: -1dBFS
Measured at LOUT_L pin
A-Weighted
min
17
typ
max
unit
1.68
V
20
23
kΩ
-80
-72
dB
16 Bits
80
86
dB
Total harmonic distortion ratio
and noise
Dynamic range
ADC_THD+N
ADC_DR
Inter-channel isolation
Inter-channel gain mismatch
PGA step width
ADC_ISO
ADC_LRG
PGA_GSTEP
PGA variable range
PGA_GVB
DAC analog output
Resolution
DAC_RES
LIN_L pin input: -1dBFS
Measured at ADC_DOUT pin
LIN_L pin input: -60dBFS
Measured at ADC_DOUT pin、
A-Weighted
LIN_L pin input,
Measured at ADC_DOUT pin
LIN_L pin input,
Measured at ADC_DOUT pin
-80
-72
dB
80
86
dB
80
100
dB
-0.5
0.5
dB
0.1
0.5
0.9
dB
-14
34
dB
16 Bits
SNR
DAC_SNR
A-Weighted
80
88
dB
Total harmonic distortion ratio
and noise
Dynamic range
DAC_THD+N
DAC_DR
Inter-channel isolation
Inter-channel gain mismatch
Output voltage
DAC_ISO
DAC_LRG
LO_V
Output load resistance
Output load capacity
Speaker Amp EVR
Gain value
LO_RL
LO_CL
EVR_G
DAC_DIN pin input: 0dBFS
Measured at LOUT_L pin
DAC_DIN pin input: -60dBFS
Measured at LOUT_L pin, A-Weighted
DAC_DIN pin input: 0dBFS
LINE_AMP gain setting =6.5dB
Measured at LOUT_L, LOUT_R pin
LOUT_L, LOUT_R pin
LOUT_L, LOUT_R pin
DAC_DIN pin input:
-6.5dBFS
Measured at SPp and
SPn pins
[EVR_GAIN]=3Fh
[EVR_GAIN]=2Fh
[EVR_GAIN]=20h
[EVR_GAIN]=10h
[EVR_GAIN]=00h
-80
-72
dB
75
88
dB
80
100
dB
-0.5
0.5
dB
1.4
2.0
2.6 dBV
10
0.0
-2.2
-7.6
-22.8
-65.2
kΩ
30
pF
dB
Speaker Amp
Total harmonic distortion ratio
and noise
Output level
SNR
Output load resistance
SP_THD+N
SP_V
SP_SNR
SP_RL
DAC_DIN pin input: 0dBFS, EVR=-2.5dB (*3)(*4)
DAC_DIN pin input: 0dBFS, EVR=-2.5dB (*4)
DAC_DIN pin input: 0dBFS, EVR=-2.5dB (*4)
SPp, SPn pin
1.0
2.0
%
2.1
3.0
3.9 dBV
78
86
dB
8
Ω
Output load capacity
SP_CL
SPp, SPn pin
30
pF
(*1) Applicable pins: Line input pin LIN_L, LIN_R
Analog input full-scale value of ADC (LI_VIN = 2.8V x 0.6)
(*2) The TYP resistance value varies from 10kΩ to 20kΩ depending on the gain setting of PGA.
(*3) Output 250mW (8Ω)
(*4) BTL converted value when the same signal has been set for Lch/Rch in the DAC input
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