72720YV Datasheet, PDF (8/14 Pages) Sanyo Semicon Device – Single-Chip RDS Signal-Processing System IC

LC72720Y, 72720YV
(3) Synchronization and RAM address reset (1 bit): SYR
SYR
0
Synchronization detection circuit
Normal operation (reset cleared)
1 Forced to the unsynchronized state (synchronization reset)
Initial value: SYR =0
RAM
Normal write (See the description of the OWE bit.)
After the reset is cleared, start writing from the data prior to the
establishment of synchronization, i.e. the data in backward protection.
Caution: 1. To apply a synchronization reset, set SYR to 1 temporarily using the CCB, and then set it back to 0 again using the CCB.
The circuit will start synchronization capture operation at the point SYR is set to 0.
2. The SYR pin (pin 24 / 30) also provides an identical reset control operation. Applications can use either method. However, the control
method
that is not used must be set to 0 at all times. Any pulse with a width of over 250 ns will suffice.
3. A reset must be applied immediately after the reception channel is changed. If a reset is not applied, reception data from the previous
channel may remain in memory.
4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding the establishment of
synchronization.
(4) RAM write control (1 bit): OWE
OWE
RAM write conditions
0 Only data for which synchronization had been established is written.
1 Data for which synchronization not has been established (unsynchronized data) is also written. (However, this applies when SYR = 0.)
Initial value: OWE = 0
(5) Error correction method setting (5 bits): EC0 to EC4
EEE
CCC
012
Number of
bits corrected
EE
CC
34
Soft-decision setting
0 0 0 0 (error detection only)
0 0 Mode 0: Hard decision
100
1 or fewer bits
1 0 Mode 1: Soft decision A
010
2 or fewer bits
0 1 Mode 2: Soft decision B
110
3 or fewer bits
11
Illegal value
001
4 or fewer bits
101
5 or fewer bits
011
Illegal value
111
Illegal value
Initial values: EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1
Caution: 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number of bits corrected is set to 0 (error
detection only). With these settings, data will be output for blocks with no errors.
2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction.
(6) Crystal oscillator frequency selection (1 bit): XS
XS = 0: 4.332 MHz
XS = 1: 8.664 MHz
Initial value: XS = 0
(7) Demodulation circuit phase control (2 bits): PL0, PL1
PL0
PL1
Demodulation circuit phase control
0
0/1 <Normal operation> when ARI presence or absence is unclear.
0
If the circuit determines that the ARI signal is absent: 90° phase
1
1
If the circuit determines that the ARI signal is present: 0° phase
Initial values: PL0 = 0, PL1 = 1
Caution: 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces the RDS data by automatically
controlling the demodulation phase with respect to the reproduced carrier. However, the initial phase following a synchronization reset is set
by PL1.
2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90° (PL1 = 0) or 0° (PL1 = 1), allowing RDS
data to be reproduced. When ARI is not present, PL1 should be set to 0, since the RDS data is reproduced by detecting at a phase of 90°
with respect to the reproduced carrier. When ARI is present, PL1 should be set to 1, since detection is at 0°. In cases where the ARI
presence is known in advance, more stable reproduction can be achieved by fixing the demodulation phase in this manner.
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