LE24CBK23MC Datasheet, PDF (7/21 Pages) Sanyo Semicon Device – Dual port EEPROM Two Wire Serial Interface(2K+2K EEPROM)

LE24CBK23MC
Pin Functions
(Bank1)
SCL1 (serial clock input) pin
The SCL1 pin is the serial clock input pin used to access the Bank1 area, and processes signals at the rising and falling
edges of the SCL1 clock signal.
This pin must be pulled up by a resistor to the VDD level, and wired-ORed with another open drain (or open collector)
output device for use.
In combine mode, the SCL1 pin functions as the serial clock input pin that controls both Bank1 and Bank2
SDA1 (serial data input/output) pin
The SDA1 pin is used to transfer serial data to the input/output of the Bank1 side area and it consists of a signal input
pin and n-channel transistor open drain output pin.
Like the SCL1 line, the SDA1 line must be pulled up by a resistor to the VDD level and wired-ORed with another
open drain (or open collector) output device for use.
(Bank2)
SCL2 (serial clock input) pin
The SCL2 pin is the serial clock input pin used to access the Bank2 area, and processes signals at the rising and falling
edges of the SCL2 clock signal.
This pin must be pulled up by a resistor to the VDD level, and wired-ORed with another open drain (or open collector)
output device for use.
In combine mode, the SCL2 pin is invalid.
SDA2 (serial data input/output) pin
The SDA2 pin is used to transfer serial data to the input/output of the Bank2 side area and it consists of a signal input
pin and n-channel transistor open drain output pin.
Like the SCL2 line, the SDA2 line must be pulled up by a resistor to the VDD level and wired-ORed with another
open drain (or open collector) output device for use.
(Common pin)
WP# (Write protection) pin
When the WP# pin is at the low level, write protection is enabled, and write is prohibited to all memory areas within
both Bank1 and Bank2. Read operation can access all memory areas regardless of the WP# pin status.
COBM# (Combine mode) pin
The COBM# pin is used to switch the EEPROM internal operation between bank mode and combine mode. The
EEPROM operates in bank mode when the COBM# pin is at the high level, and in combine mode when at the low
level. Note that in combine mode, the SCL2 and SDA2 pins are handled as don’t care.
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