LC83025E Datasheet, PDF (7/15 Pages) Sanyo Semicon Device – Digital Signal Processor for Karaoke Products

LC83025E
Specifications
Absolute Maximum Ratings at Ta = 25°C, V_SS = 0 V
Parameter
Maximum supply voltage
Output voltage
Input voltage
Peak output current
Average output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
V_DD max
Conditions
V_O1
OSC2 output
V_O2
V_IN
I_OP1
I_OP2
I_OA1
I_OA2
ΣI_OA1
ΣI_OA2
ΣI_OA3
Pd max
Topr
Tstg
Pins other than OSC2
Audio interface, external RAM interface
Microcontroller interface, P3, P4
Audio interface, external RAM interface: per pin
Microcontroller interface, P3, P4: per pin
Total for FS384O, LRCKO, BCKO, and ASO
Total for DWRT, DREAD, RAS, CAS, A3 to A8
and D0 to D7
Total for A0 to A2, SIAK, P3 and P4
Ta = –30 to +70°C
Ratings
–0.3 to +7.0
Allowed up to the
oscillator voltage.
–0.3 to V_DD + 0.3
–0.3 to V_DD + 0.3
–2 to +4
–2 to +10
–2 to +4
–2 to +10
–10 to +10
–30 to +30
–10 to +10
700
–30 to +70
–40 to +125
Unit Note
V
V
V
V
mA 1
mA 2
mA 1
mA 2
mA
mA
mA
mW
°C
°C
Allowable Operating Ranges
at Ta = –30 to +70°C, all V_DD = 4.75 to 5.25 V, all V_SS = 0 V unless otherwise specified
Parameter
Symbol
Conditions
min
typ
max
Unit Note
Operating supply voltage
Input high level voltage
Input low level voltage
Instruction cycle time
[External Clock Input Conditions]
V_DD
V_IH1
V_IH2
V_IH3
V_IL1
V_IL2
V_IL3
t_CYC
Audio interface, external RAM interface
P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5
RES, OSC1, microcontroller interface
Audio interface, external RAM interface
P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5
RES, OSC1, microcontroller interface
4.75
2.4
0.7 V_DD
0.75 V_DD
58
5.25 V
V
4
V
5
V
6
0.8 V
4
0.3 V_DD V
5
0.25 V_DD V
6
59.11 ns
Frequency
f_EXT
Pulse width
t_EXTH
t_EXTL
Rise time
t_EXTR
Fall time
t_EXTF
[Self-Excitation Oscillation Conditions]
Related to the FS384I pin. Shown in Figure 1.
max: 44.1 kHz × 384 × 1.005
min: 44.1 kHz × 384 × 0.995
16.85
23
23
17.01
9
9
MHz
ns
ns
ns
ns
Oscillator frequency
f_OSC
OSC1 and OSC2: shown in Figure 2.
44.1 kHz × 768 × ± 0.1%
33.84
33.90 MHz
Oscillator stabilization period
[Audio Data Input Conditions]
f_OSCS Shown in Figure 3.
100 ms
Transfer bit clock period
t_BCYC
354
ns
Transfer bit clock pulse width
t_BCW
Related to the BCKI and ASI pins. Shown in Figure 4.
100
ns
Data setup time
t_S
70
ns
Data hold time
t_H
70
ns
[Serial Input Clock Conditions]
Serial clock period
t_SCYC
480
ns
Serial clock pulse width
t_SCW
200
ns
Data setup time
t_SS
Related to the microcontroller interface. Shown in
70
ns
Data hold time
t_SH
Figure 5. (Related to the SICK, SI and SRDY pins.)
70
ns
SRDY hold time
t_SYH
200
ns
SRDY pulse width
t_SYW
200
ns
[DRAM Input Conditions]
Input data setup time
t_DSI
Related to external DRAM data input. Shown in Figure 6.
20
ns
Input data hold time
t_DHI
(Related to the CAS and D0 to D7 pins.)
0
ns
No. 4977-7/15