LC7940YC Datasheet, PDF (7/13 Pages) Sanyo Semicon Device – Dot-matrix LCD Drivers

Block Diagram
V1
V3
V4
VEE
M
SDI
DI3
DI2
DI1
P/S
CDI
CP
LOAD
LC7940YC, LC7941YC
01 02 03
079 080
4 Level LCD Drive Circuit
(80 bits)
80
Level Shifter (80 bits)
80
2nd Latch (80 bits)
80
1st Latch (80 bits)
4
4 bits
Data Bus
Interface
20
Address Decoder
CLK
Address Counter
(7 bits)
SER/PAR
Control
Chip Disable &
Latch Control
VDD
VSS
DISP OFF
CDO
Pin Functions
Pin No.
LC7940YC LC7941YC
91
90
86
95
87
94
92
89
89
92
88
93
l00
81
99
82
98
83
97
84
96
85
95
86
Symbol
V_DD
V_SS
V_EE
V₁
V₃
V₄
CP
CDI
LOAD
SDI
DI3
DI2
94
87
D11
I/O
Function
Supply
Supply
I
I
I
I
I
V_DD – V_SS is the logic supply.
V_DD – V_EE is the LCD supply.
LCD panel drive voltage supplies
V₁ and V_EE are selected levels.
V₃ and V₄ are not–selected levels.
Display data Input clock (falling–edge trigger).
Chip disable.
Data is read in when LOW, and not road in when HIGH.
Display data latch clock (falling–edge trigger).
On the falling edge, the LCD drive signals set by the display data are output.
Serial data input.
4–bit parallel data input pins.
Data input
SDI
LCD driver outputs
O4
O8
O80
DI3
O3
O7
O79
DI2
O2
O6
O78
DI1
O1
O5
O77
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
No. 6157—7/13