LV5608LP Datasheet, PDF (6/8 Pages) Sanyo Semicon Device – Bi-CMOS LSI For CCD Charge pump power supply

External clock signal startup sequence
LV5608LP
Set EN = H by setting V_DD
at 3 V or more.
V_DD
EN
Stop at EN = L or over-current protection
Never set V_DD at 3 V or less till the
sequence is over (7.5 ms after EN = L).
Charge pump
(C23)
Regulator
(C22)
S0
S1
SEL
Frequency selection _{Do not attempt change the signal after 9.4 ms from EN = H.}
Frequency selection _{Do not attempt change the signal after 9.4 ms from EN = H.}
External clock selected _{Do not attempt change the signal after 9.4 ms from EN = H.}
Frequency selection Do not attempt change the signal after 9.4 ms from EN = H. Frequency selection
Frequency selection _{Do not attempt change the signal after 9.4 ms from EN = H.} Frequency selection
External clock selected Do not attempt change the signal after 9.4 ms from EN = H. External clock selected
* Internal 1 MHz
SEL=L (Internal clock)
* CP clock 1MHz
* CP clock 500kHz
* CP clock 250kHz
* CP clock 125kHz
CLK
SEL=H (External clock)
* CP clock 1/2φ
* CP clock 1/4φ
* CP clock 1/8φ
* CP clock 1/16φ
* IC internal signal
Internal clock
started at 1 MHz
9.4ms(min)
Steady operation
Internal clock
Stop _{started at 1 MHz}
sequence
9.4ms(min)
7.5ms(max)
Steady operation
Stop
sequence
7.5ms(max)
EN Pin and VDD
Though the sequence operation is made at startup, startup is not effectuated if the internal circuit has not been reset.
To reset the internal circuit, it is necessary to keep the EN pin at L till VDD becomes 3V or more.
Note that operation with VDD and EN pin short-circuited cannot be made.
Since the sequence operation is incorporated for stop of operation, the charge pump remains active till 7.5ms (max)
passes after setting the EN pin to L. During this period, VDD must be kept at 3V or more to allow the internal sequence
logic to operate correctly.
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