LC78857V Datasheet, PDF (6/11 Pages) Sanyo Semicon Device – Digital Audio D/A Converter IC with On-Chip Digital Filters

LC78857V
Input Setup
1. Digital audio data input
The digital audio data is a 16-bit serial signal in an MSB-first two’s complement format. The 16-bit serial data is
input from the DATA pin to an internal register on the rising edge of the BCLK signal, and is read in on the rising
and falling edges of the LRCK signal.
Digital Audio Data Input Timing
2. Mode setup
The method used to set the speed (normal/double), deemphasis, and digital attenuator settings differs depending on
the state of the mode pin (MODE).
• When MODE is low: serial input mode
In this mode, the speed (normal/double), deemphasis, and digital attenuator settings are set by inputting serial data to
the DAT/MT pin.
<Data Format>
Attenuator data
*: The SH/EMP signal may also have the form shown by the dotted line.
Notes:DAT/MT and SH/EMP: These pins must be held fixed (low or high) at all times other than the data transfer period (t1 in the figure).
LAT/ND: This pin must be held high at all times other than during data acquisition.
• A0 (ND): Normal/double speed flag
• A1 (EMP): Deemphasis flag
A0 (ND)
L
H
Normal/double speed
Normal speed
Double speed
A1 (EMP)
L
H
Deemphasis
Off
On
The deemphasis function supports operation at fs = 44.1 kHz.
No. 5537-6/11