LC78601E Datasheet, PDF (6/11 Pages) Sanyo Semicon Device – Compact Disc Player DSP with Built-in Microcontroller

LC78601E
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Pin
DEFI
3 V/*5 V
PDO
VV_SS
ISET
VV_DD
FR
V_SS
EFMO
EFMIN
TMOD
CLV
HFL
TES
TOFF
TGL
JP
LASER
FSTA
EFBAL
SP8
V_DD
FSEQ
24
PCK
25
SLOF
26
SLED+
27
SLED–
28
PUIN
29
DOUT
30
S6
31
S5
32
S4
33
S3
34
S2
35
S1
36
COM3
37
COM2
38
COM1
39
V_SS
40
VLCD1
41
*KEYI4
42
*KEYI3
43
*KEYI2
44
*KEYI1
45
*KEYO1
46
*KEYO2
47
*RANDOM
48
RMTSL3
I/O
Function
Pin state during reset
I Defect detection signal (DEF) input. (Must be connected to 0 V if unused.)
—
I Supply voltage selection input. (High: 3V operation, low: 5V operation)
—
O
Internal VCO control phase comparator output
Undefined
—
Internal VCO ground. This pin must be connected to 0 V.
—
AI PLL circuit pins PDO output current adjustment resistor connection
—
—
Internal VCO power supply
—
AI
VCO frequency range adjustment
—
— Digital system ground. This pin must be connected to 0 V.
—
O _{Slice level}
I ^{control pins}
EFM signal output
EFM signal input
Undefined
—
I Test input. This pin must be connected to 0 V.
—
O Disc motor control output. This is a 3-value output.
Hi-Z
I Track detection signal input. This is a Schmitt input.
—
I Tracking error signal input. This is a Schmitt input.
—
O Tracking off output
High output
O Tracking gain switching output. A low level output raises the gain.
Undefined
O Track jump control output. This is a 3-value output.
Hi-Z
O Laser control. A pull-down resistor is built in.
Pulled down
O FSTA control. A pull-down resistor is built in.
Pulled down
O EFBAL control. A pull-down resistor is built in.
Pulled down
O SP8 control. A pull-down resistor is built in.
Pulled down
— Digital system power supply
—
Synchronizing signal detection output. Outputs a high level if the synchronizing signal detected
O _{from the EFM signal and the internally generated synchronizing signal match.}
Undefined
EFM data playback clock monitor. 4.3218 MHz when the phase is locked.
O (Note that this output is only provided in test mode. This pin outputs a low level during normal
mode operation.)
Low output
O Sled off control output
High output
O
Sled feed output
O
Low output
Low output
I Limit switch detection input
—
O Digital output (EIAJ format)
Undefined
O Segment output (6)
Low output
O Segment output (5)
Low output
O Segment output (4)
Low output
O Segment output (3)
Low output
O Segment output (2)
Low output
O Segment output (1)
Low output
O Common driver output (3)
Low output
O Common driver output (2)
Low output
O Common driver output (1)
Low output
— Digital system ground. This pin must be connected to 0 V.
—
— LCD drive bias 1/2 V_DD monitor
—
I Key matrix input (4). A pull-up resistor is built in.
—
I Key matrix input (3). A pull-up resistor is built in.
—
I Key matrix input (2). A pull-up resistor is built in.
—
I Key matrix input (1). A pull-up resistor is built in.
—
O Key matrix common output (1). This is an open-drain output.
Hi-Z
O Key matrix common output (2). This is an open-drain output.
Hi-Z
O Random mode indicator output (Low: random mode, high: modes other than random mode.)
Hi-Z
Remote controller identifier input (3). This pin functions as an output pin set to the low level
during resets (when the *RES pin is low) and for a few milliseconds after the *RES pin
I/O _{switches to the high level. Therefore, applications that will set this pin high must connect an}
external pull-up resistor to this pin.
Low output
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