LV23014T Datasheet, PDF (5/17 Pages) Sanyo Semicon Device – Bi-CMOS IC For Mini Component, receiver 1-chip Tuner IC Incorporating PLL

LV23014T
Description of DI control Data
No.
Control/data
Description
(1)
Programmable
• Data to set the number of divisions of programmable divider Binary value using P15 as MSB.
divider data
LSB varies depending on DVS and SNS.
(* : don’t care)
P0 to P15
DVS, SNS
DVS SNS LSB
1
*
P0
Set number of divisions (N)
272 to 65535
Actual number of divisions
Twice the set value
0
1
P0
272 to 65535
Set value
0
0
P4
4 to 4095
Set value
* LSB : P0 to P3 invalid when LSB is P4.
• Selection of the signal input (FMIN, AMIN) to the programmable divider and switching of the input
frequency.
(* : don’t care)
DVS SNS
Input
Operation frequency range
1
*
0
1
0
0
FMIN
AMIN
AMIN
10 to 160MHz
2 to 40MHz
0.5 to 10MHz
(2)
Reference
• Data to select the reference frequency.
divider data
R3 R2 R1 R0
Reference frequency
R0 to R3
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
25kHz
25kHz
25kHz
25kHz
12.5kHz
6.25kHz
3.125kHz
3.125kHz
5kHz
5kHz
5kHz
1kHz
3kHz
15kHz
PLL INHIBIT+X’tal OSC STOP
1
1
1
1
PLL INHIBIT
Related data
* PLL INHIBIT
• Programmable divider and IF counter blocks stop, FMIN, AMIN, and IFIN inputs enter the pull-down
state (GND), and the charge pump has high impedance.
(3)
IF counter
• IF counter measurement start data
IFS
control data
CTE = 1 : Count start
= 0 : Count reset
CTE
• Determines the universal counter measurement time.
GT0, GT1
GT1 GT0 Measurement time
Wait time
0
0
0
1
1
0
1
1
4ms
8ms
16ms
32ms
3 to 4ms
3 to 4ms
3 to 4ms
3 to 4ms
(4)
MUTE
• Data to determine the output of the output port IFSW, controlling the MUTE function, IF count
IF count output
output (*1), and SD time constant changeover circuit (*2).
SD time constant
“Data” = 0 : MUTE, IF count output, SD time constant changeover circuit-OFF
changeover
(during normal reception)
control data
1 : MUTE, IF count output, SD time constant changeover circuit-ON
(during search of the desired station)
IFSW
*1 : IF counter buffer output entered in the IF counter circuit of the PLL logic block
*2 : The rise time of AM-AGC voltage is shortened through rapid charge to the pin-25 external
capacity when IFSW has been set to 1.
(5)
FM/AM
• Data to determine the output of the output port BDSW, controlling switching of BAND.
BAND switch
“Data” = 0 : AM
control data
1 : FM
BDSW
Continued on next page.
No.A1205-5/17