LV1116N_08 Datasheet, PDF (5/18 Pages) Sanyo Semicon Device – Surround Processor ICs for Electronic Volume Control

I²C BUS Control Signal
tHIGH
LV1116N/1116NV
tR
tF
SCL
tLOW
tSU:STA tHD:STA
SDA
tHD:DAT
tSU:DAT
tSU:STO tBUF
Figure1 I²C BUS Control Signal timing chart
I²C BUS register
1) The explanation of I²C Bus
I²C Bus (Inter IC Bus) is the bus system which the PHILIPS company developed.
It does controls such as the start, the stop by two control signals of SDA (Serial Data) and SCL (Serial Clock).
The output of each signal is open drain and forms out of wired OR.
S: Start condition
P: Stop condition
ACK: Acknowledge
Data is transmitted in the MSB first. 1 unit is composed of 8 bits and ACK is put back from the slave to confirm.
Slave IC reads data with rising edge of SCL. Master IC changes data by falling edge in SCL.
2) The control register
Table1 Slave Address
MSB
LSB
1
1
1
0
1
1
1
0
Note; LV1116N/NV are reception exclusive use. It depends and it uses LSB by the "0" fixation.
Table2 I²C Bus transmission
Function
Input control/Gain control
Volume control
Output/Surround/MODE control
Tone control [Bass]
Tone control [TREBLE]
Sub Address
BINARY
HEX
0000 0001
01
0000 0010
02
0000 0011
03
0000 0100
04
0000 0101
05
D7 D6 D5
0
0
Channel
L+R out gain
0
0
0
0
0
0
Data
D4 D3 D2 D1 D0
Gain
Input
Volume
Surround
MODE
Bass
TREBLE
Table3 Input Selection
Sub Address
Data
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Mute
0
0
*
*
*
0
0
0
In A
0
0
*
*
*
0
0
1
0
0
0
0
0
0
0
1
In B
0
0
*
*
*
0
1
0
In C
0
0
*
*
*
0
1
1
Table4 Gain control
Sub Address
Data
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
-6dB
0
0
0
1
1
*
*
*
-4dB
0
0
0
1
0
*
*
*
0dB
0
0
0
0
0
0
0
1
0
0
0
0
0
*
*
*
+4dB
0
0
1
1
0
*
*
*
+6dB
0
0
1
1
1
*
*
*
No.8262-5/18