LC89201 Datasheet, PDF (5/9 Pages) Sanyo Semicon Device – 9600-bps Facsimile Modem

LC89201
2. DTE Interface Pins
Pin No.
29
28
27
26
25
23
22
21
20
19
18
17
16
30
32
33
34
15
Symbol
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
CSB
READB
WRITEB
IREQB
RESETB
I/O
B Data bus to host CPU
I Address bus to host CPU
I Chip select signal
I Interface memory read signal
I Interface memory write signal
O Interrupt request to host CPU
I System reset signal
Function
3. Eye Pattern Interface Pins
Pin No.
67
68
66
65
Symbol
EYECLK
EYESYNC
EYEX
EYEY
I/O
Function
O Timing clock for generating eye pattern data. This may be used as the shift clock for an external shift register.
O Eye pattern synchronization signal
O Eye pattern data serial outputs (8 bits, MSB first)
4. V.24 (RS-232C) Interface Pins
Pin No.
57
59
58
61
60
62
Symbol
RTSB
CTSB
RLSDB
TXD
RXD
DCLK
I/O
Function
I Request to send signal. The low level at this pin starts transmission; the high level suspends it.
Clear to send signal. The low level at this pin signals the availability of data for transmission; the high level indicates
O _{that the data is invalid.}
Received line signal data signal. The low level at this pin gives the timing for transferring the data received to the
O _terminal.
I Transmit data input
O Receive data output
O Transmission data clock output
5. Analog Signal Pins
Pin No.
39
44
43
40
41
42
47
46
45
49
48
Symbol
TXA
RXA
AUXIN
OPA2P
OPA2M
OPA2O
OPA1P
OPA1M
OPA1O
PGCI
PGCO
I/O
Function
O Transmitter analog output
I Receiver analog input
I Auxiliary analog input
I
I Transmission buffer input/output pins. (For details, see circuit diagram.)
O
I
I Reception buffer input/output pins (For details, see circuit diagram.)
O
I Reception gain adjustment circuit input. (For details, seecircuit diagram.)
O Reception gain adjustment circuit output.
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