LC78816MB Datasheet, PDF (5/11 Pages) Sanyo Semicon Device – 16-Bit D/A Converter for Use in Digital Audio Products

LC78816MB, 78816MC
Operation
(1) Input of digital audio data
Digital audio data is a 16-bit serial signal in an MSB first two’s complement format.
The 16-bit serial data is read into the IC from MSB on the rising edge of the BCLK signal.
The LC78816MB and 78816MC can handle various interface types.
See the timing charts for details.
DSP ICs for CD players: See timing chart (1)-x when interfacing with the LC7868KE or the 7869E.
(2) Converter operation (See Figure 1.)
The LC78816MB and 78816MC have independent D/A converter circuits for channel 1 and channel 2. These D/A
converters use a dynamic level shift conversion technique that combines resistor string (R-string DAC), PWM (pulse
width modulation), and level shifting D/A converters. After latching, the 16-bit input digital audio data (D₁₅ to D₀) is
sent to these separate D/A converters as follows:
Upper 9 bits (D₁₅ to D₇): To the R-string DAC.
Middle 3 bits (D₆ to D₄): To the PWM DAC.
Lower 4 bits (D₃ to D₀): To the level shifting DAC.
x R-string DAC
The resistor string D/A converter consists of 512 (2⁹) unit resistances (R) connected in series. The voltage applied at
the terminals of this resistor string is divided into 512 equal divisions to form the 9-bit D/A converter outputs.
The upper 9 bits of the input data value are used to select (using a switching circuit) two adjacent potentials, V1 and
V2, from the divided voltages. These are output to the PWM DAC. The relationship between these two voltages is
given by the following formula:
V2 – V1 = (VH – VL)/512
y PWM DAC
The PWM DAC is a 3-bit D/A converter that divides the interval between the two voltages, V1 and V2 output by the
R-string DAC, into 8 using PWM (pulse width modulation).
Either V1 or V2, depending on the value of the middle three bits of the data, is output to the CH1OUT (or CH2OUT)
pin.
SYSCLK is used for the PWM clock when timing chart (2)-y and (2)-z are used, and BCLK is used for all other
timing charts.
z Level Shift DAC
Two variable resistors, VRH and VRL, are connected in series at the ends of the R-string DAC resistor string to
implement a 4-bit D/A converter circuit. The variable resistors VRH and VRL operate as follows in response to the
lower 4 bits of the data value.
• Independent of the data value, the sum of the resistances (VRH + VRL) remains constant.
• According to the data value, VRH and VRL vary in the range from 0 to 15R/128 (where R is the value of the
resistors in the R-string DAC) in steps of R/128.
As a result, the R-string DAC outputs V2 and V1 vary according to the lower 4 bits of the data in steps of ∆V/128
over a range 0 to 15 × ∆V/128 (where ∆V = (VH – VL)/512).
No. 4250-5/11