LV1050M Datasheet, PDF (4/4 Pages) Sanyo Semicon Device – Dolby Pro Logic Surround Decoder

Sample Application Circuit
++ ++
LV1050M
LL--LOW, LEAK
+
+
++ ++
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
R--BPF2
1
64 ^L--BPF2
R--BPF1 ₂
S--DC--OUT ₃
10 µF
BPF
RECT
RECT
VCS LOGDIFF
PG
PG
RECT
BPF
LOGDIFF VLR
RECT
C--DC--OUT ₄
10 µF
--
+
R--DC--OUT ₅
10 µF
L--DC--OUT ₆
10 µF
VRBF ₇
220 µF
0.1 µF ^{VCC1 8}
220 µF
MIX--OUT
MIX--OUT ₉
10 µF
C--OUT
C--OUT ₁₀
10 µF
AC--GND ₁₁
220 µF
L.P.F
MIX--IN ₁₂
VREF
11PIN
A
+
B
SW5
C
VCA
VCA
VCA
VCA
S
R
R
VCA
VCA
A
SW2
B
VCA
VCA
A
L
SW1B
C
L
VOL
VOL
3PIN
59PIN
A
B
CTRIM
C
D
S MODE
4PIN
5PIN
6PIN
C--MODE
A
SW6
B
SW4^A
R
B
SW5A
B
SW5^A
L
B
CH--CONT
BPL--CONT
NOISE--FIL
NOISE--GEN
R
50 KΩ
L
50 KΩ
OSC
DEV
DELAY--IN ₁₃
DELAY--IN REVERB
FILTER
DELAY--OUT ₁₄
DELAY--OUT
L--OUT
10 µF
L--OUT ₁₅
R--OUT ₁₆
R--OUT
10 µF
LS--OUT ₁₇
LS--OUT
10 µF
RS--OUT ₁₈
RS--OUT
LFE--OUT
10 µF
LFE--OUT ₁₉
10 µF
DC OUT ₂₀
0.33 µF
DC OUT--IN ₂₁
1 µF
0.1 µF
220 µF
VCC2 ₂₂
RS--DC OUT--OUT ₂₃
1 µF
RS--DC OUT--IN ₂₄
A
B
L
C
D
+
A
--
B
R
C
D
20 KΩ
20 KΩ
20 KΩ
3
SW11 A
S
B
SW12 A
B
A
B
C
D
20 KΩ
A SW11₊
B
A SW11₊
B
VOL/MUTE
R--STEREO
DATA--DEC
A
B
B--NR
C OUT--FILTER
D
8K--SRAM
500 Hz HPF
36PIN
ADM--CONT
A
B
C
D
ADM
OSC
VDD
+
+
RS
LS
LFE--TRIM RS--TRIM LS--TRIM
VIRTUAL
VIRTUAL
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
63 ^L--BPF1
62 ^{FC--C--IN +}
61 ^RT--IN
2.2 µF
+
2.2 µF
60 ^{LT--IN +}
2.2 µF
59 ^{DC--CUT +}
47 µF
58 ^C--MODE
0.47 µF
57 ^GND1
FC--C--IN
RT--IN
LT--IN
ANALOG
56 ^NS--BPF1
22 nF
55 ^NS--BPF2
47 nF
54 ^OSC
680 pF
53 ^CLK
CLK
52 ^DATA
DATA
51 ^ENABLE
ENABLE
50 ^VSS
49 ^CR--IN
0.1 µF
DIGITAL
SVC201
15 pF
48 ^CR--OT
10 µH
47 ^LC--INE
51 pF 100 pF
46 ^LC--INB
45 ^VDD
0.1 µF
+
220 µF
44 ^A/D
82000 pF
43 ^NS
3300 pF
42 ^D/A
82000 pF
41 ^AGND
ANALOG
VCC
+
GND
+
+
+
1 µF
0.1 µF
0.1 µF
+ ++ + +
ILV00007
Notes on LV1050M Usage
• Power is supplied to the matrix and steering control circuit in the LV1050M Dolby Prologic surround decoder from
VCC1 (pin8) and GND1 (pin57). Power is supplied to the delay line circuit in the surround block from VCC2
(pin22)and GND2 (pin41), and power is supplied to the digital circuit blocks from VDD (pin45) and VSS (pin50).
• One Point that requires care is that mutual interactions (due to, for example, common impedances) between these
power supply lines may influences the signals being processed, if this happens, phenomena such as souns not being
moved smoothly may occur.
• To prevent such phenomena from occurring, observe the following recommendations.
– Design the printed circuit board layout so that all VCC and ground lines are as short and as wide as possible.
– Connect all VCC and ground lines to the power supply independently.
– Connect capacitors (about 220µF) between each of the VCC and ground pairs as close to the IC pins as possible.
Note : A sample power supply line layout is presented in the above diagram for reference.
No.6628-4/14