LE25FW403A Datasheet, PDF (4/18 Pages) Sanyo Semicon Device – 4M-bit Serial Flash Memory 30MHz SPI Bus

LE25FW403A
Table 2 Command Settings
Command
1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle Nth bus cycle
Read
03h
A23-A16
A15-A8
A7-A0
0Bh
A23-A16
A15-A8
A7-A0
X
Page erase
DBh
A23-A16
A15-A8
X
Sector erase
D8h
A23-A16
X
X
Chip erase
C7h
Page program
02h
A23-A16
A15-A8
A7-A0
PD *1
PD *1
PD *1
Page write
0Ah
A23-A16
A15-A8
A7-A0
PD *1
PD *1
PD *1
Write enable
06h
Write disable
04h
Power down
B9h
Status register read
05h
Read silicon ID
9Fh *2
Exit power down mode
ABh
Explanatory notes for Table 2
X = don't care, h = Hexadecimal notation, A23-A19 = don’t care for all commands
Even if ^CS is raised for longer than the bus cycle given in the command settings table, the command will be
recognized. However, ^CS must be raised between one bus cycle and the next.
*1. PD: Program data. Input any number of bytes of data from 1 to 256 bytes in 1-byte units.
*2. After the first bus cycle, Silicon ID repeatedly outputs 62h (manufacturer code), 11h (device code),
and 00h (dummy code).
Device Operation
The LE25FW403A features electrical on-chip erase functions using a single 3.0V power supply, that have been added
to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by
incorporating the command registers inside the chip. The read, erase, program and other required functions of the
device are executed through the command registers.
The command addresses and data are latched for program, erase and write operations.
Figures 3 and 4 show the timing waveforms of the serial data input.
First, at the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These
inputs are introduced internally starting with bit 7 in synchronization with the rising SCK edge. At this time, output pin
is in the high-impedance state. The output pin is placed in the low-impedance state when the data is output starting with
bit 7 synchronized to the falling clock edge during read, status register read and silicon ID.
The LE25FW403A supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is
automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of
SCK is high.
Figure 3 Serial Input Timing
CS
tCPH
SCK
SI
SO
tCLS
tCSS
tDS tDH
DATA VALID
High Impedance
tCLHI tCLLO tCSH
tCLH
High Impedance
SPI Mode definition
* SPI mode 0: SCK is low logic level when CS falls
* SPI mode 3: SCK is high logic level when CS falls
No.A1229-4/18