LC79400D Datasheet, PDF (4/8 Pages) Sanyo Semicon Device – Dot Matrix LCD Driver

Pin Descriptions
Pin No
90
92
83
86
85
Pin name
V_DD
V_SS
V_EE
V1
V3
84
V4
97
CP
81
CDR
100
CDL
Input/Output
Power supply
Power supply
Input
Input/Output
Input/Output
99
LOAD
93
DI4
94
DI3
95
DI2
96
DI1
Input
Input
LC79400D
Functions
V_DD and V_SS: Power supply for logic section
V_DD and V_EE: Power supply for LCD drive circuit
LCD drive level power supply
V1 and V_EE : Select level
V3 and V4 : Nonselect level
Display data shift clock (triggering on the trailing edge)
Chip disable pin
H level : Data not accepted
L level : Data accepted
Pin Name Input/Output R/L
Pin Description
CDR
Input
L Control input pin for the IC’s internal disable F/F.
CDL
CDL
Output
Input
Output pin of the IC’s internal disable F/F.
Connects to the next stage CDR pin when
establishing a cascade connection.
H Control input pin for the IC’s internal disable F/F.
CDR
Output
Output pin of the IC’s internal disable F/F.
Connects to the next stage CDL pin when
establishing a cascade connection.
Display data latch clock (triggering on the trailing edge). On the trailing
edge, output levels switch in response to the particular combination of
display data, M and DISP OFF signals.
R/L
Input data and latch address
L
H
88
M
91
R/L
1
O1
2
O2
79
O79
80
O80
Input
Input
Output
89
DISP OFF
Input
LCD drive output alternating signal
Input pin which performs input/output switching for CDR and CDL pins and
directional shift for 4-bit parallel input data.
LCD drive output
The combination of display data, M signal, and DISP OFF signal can be used
to create output levels as shown below.
M
Q
DISP OFF Output
L
L
H
V3
L
H
H
V1
H
L
H
V4
*Don’t care
H
H
H
V_EE
(To be set to either "H" or "L")
*
*
L
V1
Input pin which controls output pins O1 to O80. V1 level is output from O1 to
O80 pin output during the low level input interval (See logic table).
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