LV25450PNW Datasheet, PDF (36/40 Pages) Sanyo Semicon Device – For Automotive Applications DSP Tuner Front End

Continued from preceding page.
No.
Control block/data
(35) LSI test data
W_KEYED
(36) Sub-Address
(37) OFFSET_SW
LV25450PNW
Description
• Modifies the keyed AGC connection circuit.
1 bit
Keyed AGC switch
0
Wide + narroww
1
Narrow only
• Sub-code address
Each 1 bit
• The DC offset was given to the differential motion part of LO-OSC for the IRR
improvement, and the function to correct Duty was added.
It is control Bit to stop this function, and to switch in a state past (The offset giving is not
done).
1BITbit
Related data
Programmable Divider Structure
PLL IN
DVS
4 bits
Swallow
Counter
12 bits
fvco/N
Programmable
Divider
ferf
fvco = ferf × N
PD φE
DVS
1
0
Set divisor (N)
272 to 65535
-
Input frequency range (f (MHz))
120 ≤ f ≤ 270
-
IC internal PLL IN pin
Selected
Stopped
* : Since the IC is closed internally, the input sensitivity is not specified.
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