LV25400W Datasheet, PDF (34/42 Pages) Sanyo Semicon Device – Bi-CMOS LSI DSP Tuner Front End for Automotive Applications

LV25400W
Continued from preceding page.
No.
Control block/data
(11) 2.7V REG
ADJ
REG_ADJ0
REG_ADJ1
• Adjusts the 2.7 V regulator
2.7V REG ADJ
00
-23mV
01
(Center value)
10
+23mV
11
+64mV
Description
(12) Crystal oscillator selection • Selects the crystal element.
XS0, XS1
XS1
XS0
0
0
0
1
1
0
1
1
X’tal OSC
4.5MHz
Illegal value
Illegal value
Illegal value
(13) HD (wide) IF AGC amplifier • Corrects for sample-to-sample variations in the IF AGC amplifier gain
variation correction bits
ADJ_W0
ADJ_W1
ADJ_W2
ADJ_W3
Amount of correction : ±5 dB
4 bit
Related data
(14) DO pin control data (2)
IL0, IL1
(15) DO pin control data (1)
ULD
DT0, DT1
• Controls the DO pin output
DO pin control data (2)
IL1
IL0
IN
0
0
Open
0
1
The I3 pin state (unused)
1
0
The I2 pin state (unused)
1
1
The I1 pin state (unused)
Since there are no connected pins in the current product, the open setting must be
used.
• Determines the DO pin output.
DO pin control data (1)
ULD
IL0
DT0
DO pin
0
0
0
Low when not locked.
0
1
1
Monitor 1 (unused)
1
0
0
Monitor 2 (unused)
1
1
1
(See DO control (2))
1
0
0
Open
1
0
1
Monitor 1 (unused)
1
1
0
Monitor 2 (unused)
1
1
1
(See DO control (2))
The following item (5) must also be set when monitoring the unlock detection signal.
UL0, UL1
(16) Unlock state detection data • Selects the phase error (øE) detection width used to judge the PLL locked state.
ULD
If a phase error in excess of the øE detection width from the table below occurs, the DT0, DT1
UL0, UL1
PLL is seen as being in the unlocked state.
When the PLL is seen as being unlocked, the detection pin (DO) is set low.
UL1
UL0
φE detection width
Detection pin output
0
0
Stopped
Open
0
1
0
φE is output directly
1
0
±0.5µs
φE is delayed by 1 to 2 ms.
1
1
±1µs
φE is delayed by 1 to 2 ms.
φE
Delay
DO
1 to 2ms
Unlock state output
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No.A0633-34/42