LV76213A2F Datasheet, PDF (3/45 Pages) Sanyo Semicon Device – For PAL/NTSC Color Television Sets VIF/SIF/Y/C/Deflection /CbCr IN Implemented in a Single Chip

LV76213A2F
μ-Controller Chip Absolute maximum ratings at Ta=25°C, VSS=0V
Parameter
Maximum Supply voltage
Input voltage
Output voltage
Input/output voltage
High level
output
current
Low level
output
current
Peak output
current
Mean Output
current
Total output
current
Peak output
current
Mean output
current
Total output
Current
Symbol
VDD max
VI
VO1
VO2
VIO
IOPH
IOMH
ΣIOAH
IOPL
Pins
CpuVDD
XT1,RES#
XT2,FILT
CpuVDD2
Ports0,1
Ports04~07,1
Ports04~07,1
Ports04~07,1
Ports0,1
Conditions
VDD[V]
min
-0.3
-0.3
-0.3
-0.3
-0.3
ï½¥CMOS output
-10
ï½¥For each pin.
ï½¥CMOS output
-1
ï½¥For each pin.
The total of all
-25
pins.
For each pin
IOML1
IOML2
ΣIOAL1
ΣIOAL2
P02,P03,P06,P07
Ports1
P00,P01,P04,P05
P02,P03,P06,P07
Ports1
P00,P01,P04,P05
For each pin
For each pin
The total of all
pins.
The total of all
pins.
Limits
typ
max
unit
~
+6.0
V
~
VDD+0.3
~
VDD+0.3
~
3.3V+0.3
~
VDD+0.3
mA
20
1
8
45
16
μ-Conttoller Chip Recommended operating range at Ta=-10°C to +65°C, VSS=0V
Parameter
Operating supply
voltage range
Hold voltage
High level input
Voltage
Low level input
Voltage
Operation cycle time
(*3)
Oscillation
frequency range
Symbol
VDD
VHD
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
tCYC1
tCYC2
FmVCO1
FmVCO2
(*4)
FmRC
Pins
CpuVDD
Conditions
0.229µs≤tCYC≤200µs
VDD[V] _min.
4.5
Limits
typ.
max.
unit
5.5
V
CpuVDD
Ports0,1,
P00 port input
/interrupt
Port00
Watch-dog
timer
RES#
RAMs and the registers data are
kept in HOLD mode.
4.5 to 5.5
2.0
0.3VDD
+0.7
4.5 to 5.5 0.9VDD
4.5 to 5.5 0.75VDD
5.5
VDD
VDD
VDD
Ports0,1,
P00 port input
/interrupt
Port00
Watch-dog timer
RES#
4.5 to 5.5 VSS
4.5 to 5.5 VSS
4.5 to 5.5 VSS
0.1VDD
+0.4
0.15VDD
-0.4
0.25VDD
All functions operating
4.5 to 5.5
0.231
µs
OSD and Data slicer are not
operating
4.5 to 5.5 0.231
Built-in VCO1
4.5 to 5.5
13.0
Oscillation System clock
Built-in VCO2
OCKSEL=0 ^{4.5 to 5.5}
12.5
oscillation
OSD clock
OCKSEL=1
16.6
Built-in RC oscillation
4.5 to 5.5 0.3
1.0
200
MHz
2.0
FsX’tal
XT1(P07),
At the 32.768KHz crystal
4.5 to 5.5
32.768
KHz
(*4)
XT2(P06)
Oscillating See the figure1
Oscillation
stabilizing time
tmsVCO
ï½¥after the HOLD mode
ï½¥Power-On
4.5 to 5.5
300
mS
(Note) FLASH-ROM erase/write temperature range :Ta=25±2°C（VDD=4.5 to 5.5V）
(*3) Relational expression between Tcyc and oscillation frequency;
1/1 frequency dividing: 3/FmVCO1, 1/2 frequency dividing: 6/FVCO1.
(*4) OCKSEL is the selectable register for OSD clock frequency. (See the LC873600 users manual for details.)
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