LE28DW1621T Datasheet, PDF (3/20 Pages) Sanyo Semicon Device – 16 Megabit FlashBank Memory

16 Megabit FlashBank Memory
LE28DW1621T-80T (Draft3)
3
specific six-word loading sequence, as in the Software Data
Protect operation. After the loading cycle, the device enters into
an internally timed Erase cycle.( See Table 3 for specific codes,
Figure 5-3 for the timing waveform, and Figure 14 for a
flowchart.) During the Erase operation, the only valid reads are
Data# Polling and Toggle Bit from the selected bank, other banks
may perform normal read.
Erase Verify Mode
The LE28DW1621T provides a Erase Verify Mode in order to
improve the erase / programming cycles over ten times greater
than normal mode. The memory cell is given a optimum margin
by executing Chip erase , Block erase or Sector erase after this
mode is excecuted. The Erase Verify flow shoud be executed at
erase operation. If verify operation becomes bad, the re-erase
operation is permited within a reguration times. Refer to Fig.20
for a flowchart at Erase Verify Mode.(See Table3 for specific
codes and Fig.6 for Timing waveform)
When return to a normal mode from Erase Verify mode, the
Erase Verify Exit command should be excuted. This command
is the same as a Software ID Exit mode.(See Table 3 for specific
codes and Fig10 for Timing waveforms.)
Write Operation Status Detection
The LE28DW1621T provides two software means to detect the
completion of a Flash bank Program cycle, in order to optimize
the system Write cycle time. The software detection includes
two status bits : Data# Polling (DQ7) and Toggle Bit (DQ6). The
end of Write Detection mode is enabled after the rising edge of
WE#, which initiates the internal Erase or Program cycle.
The actual completion of the nonvolatile write is a synchronous
with the system; therefore, either a Data# Polling or Toggle Bit
read may be simultaneous with the completion of the Write
cycle. If this occurs, the system will possibly get an erroneous
result, i.e. valid data may appear to conflict with either DQ7 or
DQ6. In order to prevent spurious device rejection, if an errone-
ous result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
There is no provision to abort an Erase or Program operation,
once initiated. For the SANYO Flash technology, the associated
Erase and Program times are so fast, relative to system reset
times, there is no value in aborting the operation. Note, reads can
always occur from any bank not performing an Erase or Pro-
gram operation.
Should the system reset, while a Block or Sector Erase or Word
Program is in progress in the bank where the boot code is stored,
the system must wait for the completion of the operation before
reading that bank. Since the maximum time the system would
have to wait is 25 ms (for a Block Erase), the system ability to
read the boot code would not be affected.
Data# Polling (DQ7)
When the LE28DW1621T is in the internal Flash bank Program
cycle, any attempt to read DQ7 of the last word loaded during the
Flash bank Word Load cycle will receive the complement of the
true data. Once the Write cycle is completed, DQ7 will show true
data. The device is then ready for the next operation. (See Figure
6 for the Flash bank Data Polling timing waveforms and Figure
16 for a flowchart.)
Toggle Bit (DQ6)
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ6 will produce alternating 0's and 1's, i.e.
toggling between 0 and 1. When the Write cycle is completed,
the toggling will stop. The device is then ready for the next
operation. (See Figure 7 for Flash bank Toggle Bit timing
waveforms and Figure 16 for a flowchart.)
Data Protection
The LE28DW1621T provides both hardware and software fea-
tures to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not
initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited
when VDD is less than 1.5 volts.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will
inhibit the Write operation. This prevents inadvertent writes
during power-up or power-down.
The LE28DW1621T provides a protect area by hardware pro-
tection. The assigned address is the upper are of 2Mega bit in
Bnak1(E0000 to FFFFFh), which is set up by WP# when low.
When this operation is executed, the functions which are Sector
erase, Block erase or Word program can not be accepted.
When the Chip erase operation is executed, all area will be
erased except protected area.
Hardware Reset Function
The LE28DW1621T provides a Hardware Reset function which
set up by RESET# being low.
RESET# pin need a low puls longer than tRP. It needs a wait
priode while tRESET from Rise edge of RESET#.
The data can't be guranteed to excute the Reset operation while
write operation.
Software Data Protection (SDP)
The LE28DW1621T provides the JEDEC approved software
data protection scheme as a requirement for initiating a Write,
Erase, or Program operation. With this scheme, any Write
operation requires the inclusion of a series of three word-load
operations to precede the Word Program operation. The three-
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1³Sakata Oizumi Gunma Japan
R.1.20(4/27/2000) No.xxxx-3/20