LC87F5WC8A Datasheet, PDF (3/27 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 4096 byte on-chip 8-bit 1-chip Microcontroller

LC87F5WC8A
„ UART: 2 channels
(1) Full duplex
(2) 7/8/9 bit data bits selectable
(3) 1 stop bit (2 bits in continuous transmission mode)
(4) Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
„ AD Converter
• 8-bit × 15-channels
„ PWM
• Multifrequency 12-bit PWM × 4-channels
„ Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
(1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
(2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
„ Watchdog Timer
(1) External RC watchdog timer
(2) Interrupt and reset signals selectable
„ Clock Output Function
(1) Capable of outputting selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
(2) Capable of outputting oscillation clock of sub clock.
„ Interrupts
• 29 sources, 10 vector addresses
(1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
(2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the higher level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smaller vector
address takes precedence.
No. Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer0//base timer1
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive/ UART2 receive
8
0003BH
H or L
SIO1/SIO2/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, PWM5
10
0004BH
H or L
Port 0/T4/T5/PWM0, PWM1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smaller vector address takes precedence.
„ Subroutine Stack Levels
• 2048 levels maximum (the stack is allocated in RAM)
„ High-speed Multiplication/Division Instructions
• 16-bits × 8-bits (5 tCYC execution time)
• 24-bits × 16-bits (12 tCYC execution time)
• 16-bits ÷ 8-bits (8 tCYC execution time)
• 24-bits ÷ 16-bits (12 tCYC execution time)
No.A1898-3/27