LC877816A_08 Datasheet, PDF (3/21 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller

LC877816A/12A/08A
Continued from preceding page.
• Base Timer
1) The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
„SIO
• SIO0: 8 bit synchronous serial interface
1) LSB first/MSB first is selectable
2) Internal 8 bit baud rate generator (fastest clock period 4/3 tCYC)
3) Consecutive automatic data communication (1 to 256 bits)
• SIO1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8 bit serial I/O (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial I/O (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
„AD Converter:
• 8 bits × 9 channels
„Remote Control Receiver Circuit (connected to P73/INT3/T0IN terminal)
• Noise rejection function (noise rejection filter’s time constant can be selected from 1/32/128 tCYC)
„Watchdog Timer
• Watchdog timer can produce interrupt or system reset.
• Watchdog timer has two types.
1) Use an external RC circuit
2) Use the microcontroller’s base timer
„Interrupts
• 17 sources, 10 vectors
1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No. Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L
4
0001BH
H or L
INT3/Base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5
• Priority levels X > H > L
• For equal priority levels, vector with lowest address takes precedence.
„Subroutine Stack Levels
• 256 levels maximum (the stack is allocated in RAM)
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time)
No.A0635-3/21