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LC872G08A Datasheet, PDF (3/27 Pages) Sanyo Semicon Device – 8-bit 1-chip Microcontroller | |||
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LC872G08A/06A/04A
ÂUART
⢠Full duplex
⢠7/8/9 bit data bits selectable
⢠1 stop bit (2 bits in continuous data transmission)
⢠Built-in baudrate generator
ÂAD Converter: 12 bits/8 bits à 8 channels
⢠12 bits/8 bits AD converter resolution selectable
ÂRemote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN)
⢠Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
ÂClock Output Function
⢠Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as
the system clock.
⢠Can generate the source clock for the subclock
ÂWatchdog Timer
⢠External RC watchdog timer
⢠Interrupt and reset signals selectable
ÂInterrupts
⢠18 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0
⢠Priority levels X > H > L
⢠Of interrupts of the same level, the one with the smallest vector address takes precedence.
ÂSubroutine Stack Levels: 128levels (The stack is allocated in RAM.)
ÂHigh-speed Multiplication/Division Instructions
⢠16 bits à 8 bits
(5 tCYC execution time)
⢠24 bits à 16 bits (12 tCYC execution time)
⢠16 bits ÷ 8 bits
(8 tCYC execution time)
⢠24 bits ÷ 16 bits (12 tCYC execution time)
No.A1400-3/27
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