LC75857E Datasheet, PDF (28/39 Pages) Sanyo Semicon Device – CMOS IC 1/3, 1/4 Duty LCD Display Drivers with Key Input Function

LC75857E, LC75857W
3. Pin states during the reset period
pin
S1/P1 to S4/P4
S5 to S38
COM1 to COM3
COM4/S39
KS1/S40 to KS3/S42
KS4 to KS6
OSC
DO
State during reset
L *5
L
L
L *6
L *5
L *7
Z *8
H *9
Notes:*5. These output pins are forcibly set to the segment output function and held low.
*6. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is
transferred, either the common output or the segment output function is selected.
*7. This output pin is forcibly held fixed at the low level.
*8. This I/O pin is forcibly set to the high-impedance state.
*9. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period
even if a key data read operation is performed.
Notes on the OSC Pin Peripheral Circuit
1. RC oscillator mode (control data bit OC = 0)
When RC oscillator mode is selected, the external resistor Rosc and the external capacitor Cosc must be connected
between the OSC pin and ground.
OSC
Rosc Cosc
2. External clock mode (control data bit OC = 1)
When external clock mode is selected, the current protection resistor Rg (4.7 to 47 kΩ) must be connected between
the OSC pin and the external clock output pin (external oscillator). The value of this resistor is determined by the
allowable current for the external clock output pin. Verify that the external clock waveform is not deformed
significantly.
External clock
output pin
External oscillator
OSC
Rg
Note: The external clock output pin allowable current must be greater than VDD/Rg.
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