LC868016 Datasheet, PDF (26/28 Pages) Sanyo Semicon Device – 8-Bit Single Chip Microcontroller with 16/12/08K-Byte ROM and 640-Byte RAM On Chip

LC868016/12/08A
External data memory timing
Parameter
Symbol
RD pulse width
tRLRH
Pads and Conditions
WR pulse width
tWLWH
Data address hold time tLLAX For ADLC (at LDX)
For ADLC (at STX)
Data delay time
tRLDV From RD
Data hold time
tRHDX From RD
Data floating time
tRHDZ From RD
Data address setting
time
ADLC ! control signal
tAVLL
tLLRL
For ADLC
For RD
tLLWL For WR
Data settling time
tQVWL For WR
Data in WR =1
tQVWH
Data hold time
tWHQX From WR
Control signal ! ADLC tRHLH For RD
tWHLH For WR
Ratings
unit
VDD[V]
min.
max.
4.5 - 6.0 6tCLCL-80
ns
2.5 - 6.0 6tCLCL-320
4.5 - 6.0 6tCLCL-80
2.5 - 6.0 6tCLCL-320
4.5 - 6.0 2tCLCL-35
2.5 - 6.0 2tCLCL-140
4.5 - 6.0 2tCLCL-35
2.5 - 6.0 2tCLCL-140
4.5 - 6.0
5tCLCL-125
2.5 - 6.0
5tCLCL-400
4.5 - 6.0
0
2.5 - 6.0
0
4.5 - 6.0 2tCLCL-70 2tCLCL+70
2.5 - 6.0 2tCLCL-280 2tCLCL+280
4.5 - 6.0 tCLCL-40
2.5 - 6.0 tCLCL-160
4.5 - 6.0 3tCLCL-50 3tCLCL+50
2.5 - 6.0 3tCLCL-200 3tCLCL+200
4.5 - 6.0 3tCLCL-50 3tCLCL+50
2.5 - 6.0 3tCLCL-200 3tCLCL+200
4.5 - 6.0 tCLCL-60
2.5 - 6.0 tCLCL-240
4.5 - 6.0 7tCLCL-140
2.5 - 6.0 7tCLCL-560
4.5 - 6.0 tCLCL-50
2.5 - 6.0 tCLCL-200
4.5 - 6.0 tCLCL-50
tCLCL+50
2.5 - 6.0 tCLCL-200 tCLCL+200
4.5 - 6.0 tCLCL-50
tCLCL+50
2.5 - 6.0 tCLCL-200 tCLCL+200
Refer to figure 14.
SCLK
tCLCL
1 tCYC
ADLC
EROE
RD
Port 0
WR
Port 0
Port 2
Port 5
Port 3
tLLRL
tAVLL tLLAX
(at reading)
A7-A0
tLLWL
tRLRH
tRLDV
tWLWH
tRHDX
DATA
tRHLH
tRHDZ
Z
tWHLH
tLLAX
(at writing)
A7-A0
tQVWL
DATA
tQVWH
A15-A8
Bank
A7-A0
tWHQX
Figure 14 Timing of the external RAM
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