LC07410LG Datasheet, PDF (26/36 Pages) Sanyo Semicon Device – Monaural CODEC + Audio I/F + Video Driver

PLL Block Diagram
PLL_FCK1[2:0]
1/4
MCLKIN
1/2
1/2
24MHz
12MHz
or
13.5MHz
27MHz
PLL_DIV1
DIV1
PLL
DIV2
PLL_DIV2
LC07410LG
SEl_MCLKO
H
DIV3
PLL_PDX
EXT
PLL
1/8 (32fs)
FBCLK ^{1/4 (64fs)}
ADF_MASTER
L
1/256
CODEC
MCKOUT
LRCK
BCLK
ADRS
Bit
Name
Init
Description
0Dh
[2]
FBCLK
0b Sets the BCLK frequency
0: 64fs 1: 32fs
0Eh
[4]
ADF_MASTER
0b Sets the BCLK, LRCK master/slave
0: slave 1: master
16h
[5:4] SEL_MCLKO
00b MCLKO output selection
00: “L” 10: “H”
01/11: MCLKIN[PLL_PDX = 0] or PLL output [PLL_PDX = 1]
16h
[0]
PLL_DIV1
17h
[7:0]
07Dh
Sets the basis clock frequency ratio (DIV1)
000h: Prohibition 001h: 1/1 to 1FFh: 1/511 default: 07Dh(125)
18h
[0]
PLL_DIV2
19h
[7:0]
080h
Sets the VCO output frequency ratio (DIV2)
000h: Prohibition 001h: 1/1 to 1FFh: 1/511 default: 080h(128)
1Ah
[1:0] PLL_DIV3
00b Sets the MCLK output frequency ratio (DIV3)
00: 1/1 01: 1/2 10: 1/4 11: 1/4
[5:4] PLL_FCKI
00b Sets the MCLKIN input frequency ratio
00: 1/1 01: 1/2 10: 1/4 11: 1/4
Frequency Ratio Setting Example
Target frequency
fs(kHz)
256fs(MHz)
48
12.288
44.1
11.29
32
8.192
24
6.144
22.05
5.6448
16
4.096
12
3.072
11.025
2.8224
8
2.048
DIV1
125
304
271
125
304
271
125
304
271
DIV1 input = 12MHz
Frequency Ratio Value
DIV2
128
286
185
128
286
185
128
286
185
DIV3
1
1
1
2
2
2
4
4
4
DIV1
245
171
206
245
171
206
245
171
206
DIV1 input = 13.5MHz
Frequency Ratio Value
DIV2
223
143
125
223
143
125
223
143
125
DIV3
1
1
1
2
2
2
4
4
4
No.A1345-26/36