LC786800E Datasheet, PDF (22/26 Pages) Sanyo Semicon Device – Compressed Audio signal Processor IC with USB host controller

PLL circuit
Example of PLL circuit
LC786800E
LC786800
VVDD3
VVDD2
AFILT
Cp2
Rp1
Cp1
• PLL
LC786800 includes PLL1 and PLL2.
The functions of PLL1/ PLL2 varies depends on the oscillator connected to XIN/XOUT.
PLL1
PLL2
When 12MHz oscillator is used
For system clock generation
For audio clock generation
When 16.9344MHz oscillator is used
Unused
For system clock generation
• External filter constant for PLL2
When 12MHz oscillator is used
When 16.9344MHz oscillator is used
PLL2 constant
Rp1 = 4.7kΩ/Cp1 = 3300pF/Cp2 = 220pF
Rp1 = 4.7kΩ/Cp1 = 0.033μF/Cp2 = 2200pF
<Caution>
• This PLL filter circuit is for resistor (Rp1), capacitance (Cp1, Cp2), audio generation/ system clock generation
connected to AFILT. If oscillation clock is disturbed by noise or by the other factors, it may lead to operation failure.
Hence, make sure to connect resistor and capacitor that constitute filter circuit as close as AFILT and the wire
should be as short as possible. Also if filter constant changes due to temperature change, oscillation of PLL may
become unstable and the following problem may occur.
(1) 12MHz oscillator
Due to unstable audio playback clock, audio playback is affected with unstable audio signal input (ADC
operation) and output (various filter, DAC operation).
(2) 16.9344MHz oscillator
As the internal system clock used in built-in CPU and USB becomes unstable, the LSI operation is affected as
well.
Hence, you need to select parts with caution so as to obtain stable filter constant value within the guaranteed
operating temperature range.
• See the section on “Analog Pin Internal Equivalent Circuits” for the internal configuration of AFILT.
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