LC895297 Datasheet, PDF (2/9 Pages) Sanyo Semicon Device – Full CAV 20 x CD-ROM Decoder with Built-in ATA-PI (IDE) Interface and CD-DSP

LC895297
Specifications
Absolute Maximum Ratings at Ta = 25°C, V_SS = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
Input and output voltage
Allowable power dissipation
Operating temperature
V_DD max
V_I, V_O
Pd max
Topr
Ta ≤ 70°C *1
–0.3 to +7.0
V
–0.3 to V_DD+0.3
V
500
mW
–30 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Soldering conditions (pins only)
10s
235
°C
Input and output current
I_I, I_O
Per individual input or output cell
±20
mA
Note 1: Applications that use this IC must adopt heat dissipation measures, such as the insertion of a thermally conductive sheet.
Allowable Operating Ranges at Ta = –30 to +70°C, V_SS = 0 V
Parameter
[Input and Output Cell Power Supply]
Supply voltage
Input voltage range
[Internal Cell Power Supply]
Supply voltage
Input voltage range
Symbol
V_DD
V_IN
V_DD
V_IN
Conditions
Ratings
Unit
min
typ
max
4.5
5.0
5.5
V
0
V_DD
V
3.9
4.0
4.1
V
0
V_DD
V
Electrical Characteristics at Ta = –30 to +70°C, V_SS = 0 V, V_DD = 4.5 to 5.5 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input high-level voltage
Input low-level voltage
V_IH
2.2
TTL levels. Applicable pins: (10) and (13)
VIL
V
0.8
V
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Input high-level voltage
Input low-level voltage
Output high-level voltage
V_IH TTL levels. Applicable pins: (1)
2.2
V_IL Pull-up resistor included.
V_IH TTL levels. Applicable pins: (2), (3), and (15)
2.4
V_IL Schmitt inputs.
V_IH CMOS levels: Applicable pins: (14)
0.7 V_DD
V_IL
V_IH CMOS levels: Applicable pins: (4)
0.8 V_DD
V_IL Schmitt inputs.
V_OH
I_OH = –2 mA: Applicable pins: (5), (1), (9),
(10), and (15)
V_DD – 2.1
V
0.8
V
0.8
V
V
0.3 V_DD
V
V
0.2 V_DD
V
V
Output low-level voltage
V_OL
I_OL = 2 mA: Applicable pins: (5), (1), (9),
(10), and (15)
0.4
V
Output high-level voltage
Output low-level voltage
Output low-level voltage
Output low-level voltage
Input leakage current
V_OH I_OH = –4 mA: Applicable pins: (3) and (6)
V_DD – 2.1
V_OL I_OL = 24 mA: Applicable pins: (3) and (6)
V_OL I_OL = 2 mA: Applicable pins: (7) and (11)
V_OL I_OL = 24 mA: Applicable pins: (12)
I_IL
V_I = V_SS, V_DD: Applicable pins: (2), (3), (4),
(10), and (15)
–10
V
0.4
V
0.4
V
0.4
V
+10
µA
Output leakage current
In high-impedance output mode: Applicable
I_OZ
pins: (3), (6), (7), (9), (10), (12), and (15)
–10
+10
µA
Pull-up resistance
R_UP Applicable pins: (1) and (11)
40
80
160
kΩ
The applicable pin sets are as follows:
[INPUT]
(2) ZRESET, ZDMACK, ZHRST, DA0to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, FG
(4) ZCSCTRL, ZCS, ZRD, ZWR, HFL, TES
(14) DEFI
(13) SUA0 o SUA6
[OUTPUT]
(6) DMARQ, HINTRQ
(5) RA0 to RA8, ZRAS0, ZCAS0, ZOE, ZUWE, ZLWE, C2F, ROMXA, FSX, EFLG, PCK, FSEQ, TOFF, TGL, 4.2M, WRQ, RWC, COIN, ZCQCK, RCHP,
RCHN, LCHP, LCHN
(7) ZRSTCPU, ZRSTIC
(9) JP⁺, JP^–, SPO
(11) ZINT0, ZINT1, ZSWAIT
(12) IORDY, ZIOCS16
Continued on next page.
No. 5785-2/9