LB11696V Datasheet, PDF (2/16 Pages) Sanyo Semicon Device – Direct PWM Drive Brushless Motor Predriver IC

LB11696V
Allowable Operating Ranges at Ta = 25°C
Parameter
Supply voltage range 1-1
Supply voltage range 1-2
Output current
5 V constant voltage output current
HP pin applied voltage
HP pin output current
RD pin applied voltage
RD pin output current
Symbol
V_CC1-1
V_CC1-2
I_O
IREG
VHP
IHP
VRD
IRD
Conditions
V_CC pin
V_CC pin, when V_CC is shorted to VREG.
UL, VL, WL, UH, VH, and WH pins
Ratings
Unit
8 to 17
V
4.5 to 5.5
V
25
mA
–30
mA
0 to 17
V
0 to 15
mA
0 to 17
V
0 to 15
mA
Electrical Characteristics at Ta = 25°C, V_CC = 12 V
Parameter
Current drain 1
Current drain 2
[5 V Constant Voltage Output (VREG pin)]
Output voltage
Line regulation
Load regulation
Temperature coefficient
[Output Block]
Output voltage 1-1
Output voltage 1-2
Output voltage 2
Output leakage current
[Hall Amplifier Block]
Input bias current
Common-mode input voltage range 1
Common-mode input voltage range 2
Symbol
I_CC1
I_CC2
Stop mode
Conditions
Ratings
Unit
min
typ
max
12
16 mA
2.5
4 mA
VREG
∆VREG1
∆VREG2
∆VREG3
V_CC = 8 to 17 V
I_O = –5 to –20 mA
Design target value
4.7
5.0
5.3
V
40
100 mV
10
30 mV
0
mV/°C
V_OUT1-1
V_OUT1-2
V_OUT2
I_Oleak
Low level, I_O = 400 µA
Low level, I_O = 10 mA
High level, I_O = –20 mA
0.2
0.9
V_CC – 1.1 V_CC – 0.9
0.5
V
1.2
V
V
10 µA
IHB (HA)
VICM1
VICM2
When a Hall effect device is used
Single-sided input bias mode (when a Hall IC
is used)
–2
–0.5
µA
0.5
V_CC – 2.0
V
0
V_CC
V
Hall Input Sensitivity
Hysteresis
Input voltage low → high
Input voltage high → low
[CTL Amplifier]
Input offset voltage
Input bias current
Common-mode input voltage range
High-level output voltage
Low-level output voltage
Open-loop gain
[PWM Oscillator (PWM pin)]
High-level output voltage
Low-level output voltage
External capacitor charge current
Oscillator frequency
Amplitude
[TOC pin]
Input voltage 1
Input voltage 2
Input voltage 1 low
Input voltage 2 low
Input voltage 1 high
Input voltage 2 high
[HP Pin]
Output saturation voltage
Output leakage current
∆VIN (HA)
VSLH (HA)
VSHL (HA)
80
15
24
5
12
–20
–12
mVp-p
40 mV
20 mV
–5 mV
V_IO (CTL)
I_B (CTL)
VICM
V_OH (CTL)
V_OL (CTL)
G (CTL)
ITOC = –0.2 mA
ITOC = 0.2 mA
f (CTL) = 1 kHz
–10
10 mV
–1
1 µA
0
VREG – 1.7
V
VREG – 1.2 VREG – 0.8
V
0.8
1.05
V
45
51
dB
V_OH (PWM)
V_OL (PWM)
ICHG
f (PWM)
V (PWM)
VPWM = 2.1 V
C = 2000 pF
2.75
3.0
3.25
V
1.2
1.35
1.5
V
–120
–90
–65 µA
22
kHz
1.4
1.6
1.9 Vp-p
VTOC1 Output duty: 100%
2.68
3.0
3.34
V
VTOC2 Output duty: 0%
1.2
1.35
1.5
V
VTOC1L Design target value, when VREG = 4.7 V, 100%
2.68
2.82
2.96
V
VTOC2L Design target value, when VREG = 4.7 V, 0%
1.23
1.29
1.34
V
VTOC1H Design target value, when VREG = 5.3 V, 100%
3.02
3.18
3.34
V
VTOC2H Design target value, when VREG = 5.3 V, 0%
1.37
1.44
1.50
V
VHPL
IHPleak
I_O = 10 mA
V_O = 18 V
0.2
0.5
V
10 µA
Continued on next page.
No.8087-2/16