LC871HC4A Datasheet, PDF (19/27 Pages) Sanyo Semicon Device – CMOS IC 128K/96K-byte ROM and 12288-byte RAM integrated 8-bit 1-chip Microcontroller with USB-host controller

LC871HC4A/92A
4. SIO9 Serial I/O Characteristics (Note 4-4-1)
Parameter
Frequency
Low level
pulse width
High level
pulse width
Frequency
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
Symbol
tSCK(7)
tSCKL(7)
Pin/
Remarks
SCK9(P27)
Conditions
See Fig. 8.
tSCKH(7)
tSCKHA(7a)
tSCKHA(7b)
tSCKHA(7c)
tSCK(8)
tSCKL(8)
tSCKH(8)
tSCKHA(8a)
tSCKHA(8b)
tSCKHA(8c)
tsDI(4)
thDI(4)
SO9(P25),
SI9(P26)
• USB, SIO0 continuous transfer
mode, AIF, SIO4 and DMCOPY
not used at the same time.
• See Fig. 8.
• (Note 4-4-2)
• USB used at the same time.
• SIO0 continuous transfer mode,
AIF, SIO4, and DMCOPY not
used at the same time.
• See Fig. 8.
• (Note 4-4-2)
• USB, SIO0 continuous transfer
mode, SIO4 and DMCOPY used
at the same time.
• AIF not used at the same time.
• See Fig. 8.
• (Note 4-4-2)
• When CMOS output type is
selected.
• See Fig. 8.
• USB, SIO0 continuous transfer
mode, AIF SIO4 DMCOPY not
used at the same time.
• When CMOS output type is
selected.
• See Fig. 8.
• USB used at the same time.
• SIO0 continuous transfer mode,
AIF, SIO4, and DMCOPY not
used at the same time.
• When CMOS output type is
selected
• See Fig. 8.
• USB, SIO0 continuous transfer
mode , SIO4, and DMCOPY
used at the same time.
• AIF not used at the same time.
• When CMOS output type is
selected.
• See Fig. 8.
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 8.
VDD[V]
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
min
2
1
1
4
7
15
4/3
tSCKH(8)
+
(5/3)tCYC
tSCKH(8)
+
(5/3)tCYC
tSCKH(8)
+
(5/3)tCYC
0.03
0.03
Specification
typ
max
unit
tCYC
1/2
tSCK
1/2
tSCKH(8)
+
(10/3)tCYC
tSCKH(8)
+
(19/3)tCYC
tCYC
tSCKH(8)
+
(43/3)tCYC
Output delay time tdDO(6)
SO9(P25), • Must be specified with respect
μs
SI9(P26)
to falling edge of SIOCLK.
• Must be specified as the time to
the beginning of output state
2.7 to 5.5
(1/3)tCYC
+0.05
change in open drain output mode
• See Fig. 8.
Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating
conditions.
Note 4-4-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the time
from SI9RUN being set when serial clock is high to the falling edge of the first serial clock must be longer
than tSCKHA.
No.A1188-19/27