LC87F7DC8A_10 Datasheet, PDF (18/26 Pages) Sanyo Semicon Device – FROM 128K byte, RAM 4K byte on-chip 8-bit 1-chip Microcontroller

LC87F7DC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
Conditions
SCK1(P15)
See Fig. 6.
Low level
pulse width
High level
pulse width
Frequency
Low level
pulse width
High level
pulse width
Data setup time
Data hold time
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
thDI(2)
SCK1(P15)
• CMOS output selected
• See Fig. 6.
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
SIOCLK.
• See Fig. 6.
VDD[V]
2.2 to 5.5
2.2 to 5.5
min
2
Specification
typ
max
1
1
2
1/2
1/2
unit
tCYC
tSCK
2.2 to 5.5
0.03
2.2 to 5.5
0.03
Output delay time tdD0(4)
SO1(P13),
• Must be specified with
SB1(P14)
respect to falling edge of
SIOCLK.
• Must be specified as the
time to the beginning of output
2.2 to 5.5
state change in open drain
output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
μs
(1/3)tCYC
+0.05
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
High/low level
Symbol
tPIH(1)
Pin/Remarks
INT0(P70),
Conditions
• Interrupt source flag can be set.
Specification
VDD[V]
min
typ
max
unit
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72),
are enabled.
INT4(P30 to P33),
2.2 to 5.5
1
INT5(P34 to P35),
INT6(P30),
INT7(P34)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
constant is 1/1
• Event inputs for timer 0 are
enabled.
2.2 to 5.5
2
tCYC
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
2.2 to 5.5
64
constant is 1/32
enabled.
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
2.2 to 5.5
256
constant is 1/128
enabled.
tPIH(5)
tPIL(5)
MICIN(P87)
Condition that signal is accepted to
2.2 to 5.5
1
small signal detection counter.
tPIH(6)
tPIL(6)
RMIN(P73)
Condition that signal is accepted to
2.2 to 5.5
4
remote control receiver circuit.
RMCK
(Note5-1)
tPIL(7)
RES
Resetting is enabled.
2.2 to 5.5
200
μs
Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit.
No.A1156-18/26