LB11921T Datasheet, PDF (14/18 Pages) Sanyo Semicon Device – Monolithic Digital IC Three-Phase Brushless Motor Driver

LB11921T
LB11921T Overview
1. Speed Control Circuit
This IC implements speed control using the combination of a speed discriminator circuit and a PLL circuit. The
speed discriminator circuit outputs (This counts a single FG period.) an error signal once every two FG periods. The
PLL circuit outputs an error signal once every one FG Period. As compared to the earlier technique in which only a
speed discriminator circuit was used, the combination of a speed discriminator and a PLL circuit allows variations in
motor speed to be better suppressed when a motor that has large load variations is used. The FG servo frequency
(fFG) is controlled to have the equal frequency with the clock signal (fCLK) which is input through the CLK pin.
fFG = fCLK
2. VCO Circuit
The LB11921T includes a built-in VCO circuit to generate the speed discriminator circuit reference signal. The
reference signal frequency is given by the following formula.
fVCO = fCLK × 512
fVCO: Reference signal frequency
fCLK: Externally input clock frequency
The range over which the reference signal frequency can be varied is determined by the resistor and capacitor
components connected to the R and C pins (pins 14 and 15) and by the VCO loop filter constant (the values of the
external components connected to pin 13).
Reference value at VCC = 5V
fFG in the high-speed
rotation mode
R(kΩ)
1.5kHz
5.6
2.0kHz
5.6
C(pF)
330
220
The components connected to the R, C, and FIL pins must be connected with lines to their ground pin (pin 23) that
are as short as possible.
3. Output Drive Circuit
To reduce power loss in the output, this IC adopts the direct PWM drive technique. The output transistors (which are
external to the IC) are always saturated when on, and the motor drive output is adjusted by changing the duty with
which the output is on. The PWM switching is performed on the UH, VH, and WH pins. The PWM switching side in
the output can be selected to be either the high or low side depending on how the external transistors are connected.
4. Current Limiter Circuit
The current limiter circuit limits the (peak) current at the value I = VRF/Rf (VRF = 0.26V (typical), Rf: current
detection resistor). The current limitation operation consists of reducing the output duty to suppress the current.
High accuracy detection can be achieved by connecting the RF and RFGND pin lines near the ends of the current
detection resistor (Rf).
5. Speed Lock Range
The speed lock range is ±6.25% of the fixed speed. When the motor speed is in the lock range, the LD pin (an open
collector output) goes low. If the motor speed goes out of the lock range, the motor on duty is adjusted according to
the speed error to control the motor speed to be within the lock range.
6. Notes on the PWM Frequency
The PWM frequency is determined by the capacitor (F) connected to the PWM pin.
fPWM ≈ 1/(64000 × C)
A PWM frequency of between 15 and 25kHz is desirable. If the PWM frequency is too low, the motor may resonate
at the PWM frequency during motor control, and if that frequency is in the audible range, that resonation may result
in audible noise. If the PWM frequency is too high, the output transistor switching loss will increase. To make the
circuit less susceptible to noise, the connected capacitors must be connected to the GND pin (pin 23) with
lines that are as short as possible.
No.A0604-14/18