LC749880T Datasheet, PDF (13/17 Pages) Sanyo Semicon Device – Silicon gate Image controller LSI for LCD-TV

LC749880T
A/D Convertor Characteristics at Ta = -30 to +70°C, DVSS = 0V, AVSS = 0V
Clock frequency
Parameter
Symbol/pin
min
Fclk
Clamp pulse width
External capacitance
Tcl
0.45
Analog input coupling capacitance
Top level reference fixed capacitance
Analog video pin
0.01
VRTx pin
Bottom level reference capacitance
VRBx pin
VREF1 bias fixed capacitance
VREF1 pin
NBIAS bias fixed capacitance
NBIAS pin
Analog input frequency
FAIN
Analog input amplitude (Max amplitude)
In the non-AGC operation mode
FS1AIN
In the AGC operation mode *1
ADC reference input voltage
FS2AIN
0.6
In the non-AGC operation mode
Bottom level reference input
VRBI
In the AGC operation mode
Bottom level reference input
VRBI
typ
0.01
0.01
0.01
0.01
0.65
0.65
max
27
Unit
MHz
μs
10
μF
μF
μF
μF
μF
4
MHz
1.0
Vp-p
1.1
Vp-p
V
V
DC Characteristics at Ta=25°C, VDD3=3.3V±5%,VDD=1.8V±5%, DVSS = 0V, AVSS = 0V
Parameter
Operating supply current
3.3V power supply
1.8V power supply
Standby supply current
3.3V power supply
1.8V power supply
Symbol
IDD3
IDD
ISB3
ISB
Conditions
VDD3=3.3V
VDD=1.8V
Fclk=27MHz
VDD3=3.3V
VDD=1.8V
Fclk=0MHz
min
-10
-10
typ
16
16
max
Unit
mA
mA
+10
μA
+10
μA
ADC Conversion Characteristics at Ta=25°C,VDD3=3.3V±5%,VDD=1.8V±5%, DVSS = 0V, AVSS = 0V
Parameter
Resolution
Symbol
RES
Conditions
min
typ
max
Unit
10
bits
I/O Data Timing
(1) Input data timing 1
XIN
tSU
Input data
tHI
tCK
VDD33/2
tLO
tHD
VDD33/2
Pin name
Parameter
Symbol
min
max
Unit
XIN
Clock L-level time
tLO
18.5
ns
Clock H-level time
tHI
18.5
ns
Clock cycle
tCK
37
ns
VP24-34
Input data setup time
tSU
3.5
ns
POL, FLM, OE, CPV, STRB
SP, DEXR
Input data hold time
tHD
3.5
ns
RIN, GIN, BIN, BLKIN
* The recommended duty ratio of input clock is 50%
No.A1186-13/17