LB11870_07 Datasheet, PDF (13/14 Pages) Sanyo Semicon Device – For Polygonal Mirror Motors Three-Phase Brushless Motor Driver

LB11870
10. Phase Lock Signal
(1) Phase lock range
Since this IC does not include a counter or similar functionality in the speed control system, the speed error range
in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of
the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the
motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in
states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in
at startup and when unlocked due to switching clock frequencies.
(2) Masking function for the phase lock state signal
A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock
pullin. However, this results in the lock state signal output being delayed by the masking time.
The masking time is determined by the capacitor inserted between the CLD pin and ground.
<masking time (seconds)> ≈ 0.9 × C (μF)
When a 0.1μF capacitor is used, the masking time will be about 90ms. In cases where complete masking is
required, a masking time with fully adequate margin must be used. If no masking is required, leave the CLD pin
open.
11. Power Supply Stabilization
Since this IC provides a large output current and adopts a switching drive technique, the power supply line level can
be disrupted easily. Thus capacitors large enough to stabilize the power supply voltage must be inserted between the
VCC pins and ground. The ground leads of these capacitors must be connected to the three pins that are the power
grounds, and they must be connected as close as possible to the pins themselves. If these capacitors (electrolytic
capacitors) cannot be connected close to their corresponding pins, ceramic capacitors of about 0.1μF must be
connected near these pins.
If reverse torque control mode is selected for use during deceleration, since there are states where power is returned
to the power supply system, the power supply line levels will be particularly easily disrupted. Since the power line
level is most easily disrupted during lock pull-in at high motor speeds, this state needs extra attention; in particular,
capacitors that are adequately large to handle this situation must be selected.
If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected
with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors
must be used.
12. VREG Stabilization
A capacitor of at least 0.1μF must be used to stabilize the VREG voltage, which is the control circuit power supply.
The ground lead of that capacitor must be connected as close as possible to the IC control system ground (GND1).
13. Error Amplifier External Component Values
To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC
as possible. In particular, they must be located as far from the motor as possible.
14. FRAME Pin and the IC Metallic Rear Surface
The FRAME pin must be connected to the GND1 and GND2 pins, and the ground side of the electrolytic capacitor
must be connected to GND3. The IC's metallic rear surface is connected to the FRAME pin internally to the IC.
Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC
package to the PCB with, for example, a solder with good thermal conductivity.
No.7256-13/14