LC72144M Datasheet, PDF (12/22 Pages) Sanyo Semicon Device – PLL Frequency Synthesizer

LC72144M
Continued from preceding page.
Control section/
No. _data
Function
Data that selects the input pin (HCTR or LCTR) for the general-purpose counter
CTS1
1
0
0
CTS0
!
1
0
Input pin
HCTR
LCTR
LCTR
Measurement mode
Frequency
Frequency
Period
Data that specifies the start of a general-purpose counter measurement operation
CTE = 1: Count start
= 0: Count reset
General-
Data that determines the general-purpose counter measurement time (in frequency mode) and number
purpose
of periods (in period mode)
counter control
(6)
data
CTS0, CTS1,
GT1
CTE, GT0, GT1
Frequency measurement mode
GT0
Measurement time
Wait time (ms)
Period measurement
mode
(ms)
CTP = 0 CTP = 1
CTP, CTC
0
0
4
3 to 4
1 to 2
1 period
0
1
8
3 to 4
1 to 2
1 period
1
0
32
7 to 8
1 to 2
2 periods
1
1
64
7 to 8
1 to 2
2 periods
CTP = 0: The general-purpose counter input is pulled down at count reset time (when CTE = 0).
= 1: The wait time is shortened by not pulling down the general-purpose counter input count reset
time (when CTE = 0). However, immediately after CTP is set to 1, the system must wait until
the general-purpose counter input pin is biased before starting a count.
The input sensitivity is lowered by setting CTC to 1. (Sensitivity: 10 to 30 mVrms)
Data that specifies the input or output state of the I/O ports
I/O port control Data value = 0: Input port
(7)
data
= 1: Output port
I/O-0 to I/O-5 ^{Note: I/O-0, I/O-1, I/O-2, I/O-4, and I/O-5 are set to function as input ports after the power on reset.}
I/O-3 is set to function as an output port after the power on reset.
Data that determines the output values of output ports O-0 to O-5
Output port Data value = 1: Open or high
(8)
data
= 0: Low
OUT0 to OUT5 ^{Note: This data is invalid when the corresponding port is specified to function as an input port or as an}
unlock state output.
General-
Data that sets the general-purpose counter pins to function as input ports
purpose
H/I-6 = 0: I-6 (input port)
(9) ^{counter input}
= 1: HCTR (general-purpose counter)
control data _{L/I-7 = 0: I-7 (input port)}
H/I-6, L/I-7
= 1: LCTR (general-purpose counter)
Data that selects the phase error (øE) detection width used for PLL lock state discrimination
If a phase error in excess of the øE detection width listed in the table below is detected, the system
considers a phase error to have occurred and the PLL to be in the unlocked state. The detection pin
(DO or I/O-5) is set low in the unlocked state.
UL1
UL0
0
0
0
1
Unlock
1
0
(10) ^{detection data}
1
1
UL0, UL1
øE detection width
Stopped
0
±0.5 µs
±1.0 µs
Detection pin output
Open
øE output
øE with 1 to 2 ms expansion
øE with 1 to 2 ms expansion
Related data
H/I-6, L/I-7
OUT0 to OUT5, ULD
I/O-0 to I/O-5, ULD
CTS0, CTS1
ULD, DT0, DT1
I/O-5
1 to 2 ms
Expansion
Unlock state output
Continued on next page.
No. 5377-12/22