LV5230LG_10 Datasheet, PDF (11/27 Pages) Sanyo Semicon Device – 7ch x 17ch LED Driver

LV5230LG
Data transfer and acknowledgement response
After establishment of start conditions, data transfer is made by one byte (8 bits).
Data transfer enables continuous transfer of any number of bytes.
Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side.
The ACK signal is issued when SDA on the send side is released and SDA on the receive side is set “L” immediately
after fall of the clock pulse at the SCL eighth bit of data transfer to “L”.
When the next 1-byte transfer is left in the receive state after transmission of the ACK signal from the receive side,
the receive side releases SDA at fall of the SCL ninth clock.
In the I²C bus, there is no CE signal. Instead, 7-bit slave address is assigned to each device and the first byte of
transfer is assigned to the command (R/W) representing the 7-bit slave address and subsequent transfer direction.
The 7-bit address is transferred sequentially from MSB and if the eighth bit is “L”, the second byte is WRITE mode
and if “H”, the second byte is READ mode.
In the READ mode, the ACK signal issued immediately before sending the stop condition must be 1.
In LV5230, the slave address is specified as (1110111).
Write mode
Start
M
S
Slave address
L
S
A
WC
M
S
Register address
L
S
A
C
M
S
B
B
KB
BKB
Data
LA
SC
BK
Stop
SCL
SDA
1110111
00000010
00010001
Read mode
Start
M
S
Slave address
L
S
A
WC
M
S
B
B
KB
Data
LAM
SCS
BKB
Data
LA
SC
BK
Stop
SCL
SDA
1110111 1
STATUS
0
STATUS
1
No.A1359-11/27