LC78011E Datasheet, PDF (11/13 Pages) Sanyo Semicon Device – Digital RGB Encoder IC for Video CD and CD-G

LC78011E
Functional Description
1. Clocks
The system clock operates at 4fsc and is input to the CLKI pin (pin 6). A feedback (bias) resistor is built in.
Input clock frequencies:
NTSC mode: 14.31818 MHz
PAL mode: 17.734475 MHz
PAL-M mode: 14.30244596 MHz
2. Video signal output formats
The LC78011E can provide either a Y/C (luminance signal/chrominance signal) separated signal output or a
composite video signal output.
The CCSEL pin (pin 30) selects the output format.
CCSEL (pin 30) setting
CROUT (pin 26) output
YOUT (pin 28) output
High = 1
Composite video signal
Fixed low-level output
(The D/A converter is stopped.)
Low = 0
Chroma signal (C)
Luminance signal (Y)
3. Digital video input switching
The LC78011E supports both input from an MPEG decoder (24 bits, 8 bits each of R, G, and B data) and a 12-bit
CD-G input (4 bits each of R, G, and B data). The CDGSEL pin (pin 33) switches the input.
CDGSEL (pin 33)
Digital input selection
Low = 0
12-bit input (CD-G)
High = 1
24-bit input (Video CD)
• Sample CD-G (LC7874E) connection
LC78011E
LC7874E
RYIN7 (pin 45) ROUT3 (pin 36)
RYIN6 (pin 46) ROUT2 (pin 37)
R
RYIN5 (pin 47) ROUT1 (pin 38)
RYIN4 (pin 48) ROUT0 (pin 39)
GUIN7 (pin 9) GOUT3 (pin 42)
GUIN6 (pin 10) GOUT2 (pin 43)
G
GUIN5 (pin 11) GOUT1 (pin 44)
GUIN4 (pin 12) GOUT0 (pin 45)
BVIN7 (pin 17) BOUT3 (pin 46)
BVIN6 (pin 18) BOUT2 (pin 47)
B
BVIN5 (pin 19) BOUT1 (pin 48)
BVIN4 (pin 20) BOUT0 (pin 49)
4. Digital video input format selection
The LC78011E supports both RGB and YUV formats. The YUVSEL1 and YUVSEL2 pins (pins 43 and 44) are
used to select the input video format.
YUVSEL2 (pin 44) YUVSEL1 (pin 43)
Input format
Low = 0
Low = 0
RGB input
Low = 0
High = 1
YUV input
High = 1
Low = 0
Y/UV input*
High = 1
High = 1
Illegal value
Note :* GUIN0 to GUIN7 are not used in the Y/UV input mode.
The U/V discrimination for the UV input is performed by starting acquisition of the U input data with a timing referenced to the falling edge of
the BLANK pin (pin 40) input signal. In this mode, the input pins GUIN0 to GUIN7 must be left open or tied to DVSS. (These inputs include
built-in pull-down resistors.)
No. 5755-11/13