LE25LA642CS Datasheet, PDF (10/14 Pages) Sanyo Semicon Device – 64Kbit Serial SPI EEPROM

LE25LA642CS
BP0, BP1 (bits2, 3)
Block Protect Settings
Block protect BP0 and BP1 are status register bits that can be rewritten, and the memory space to be protected can be
set depending on these bits. For the setting conditions, refer to “Table 3 Protect Level Setting Conditions.”
Table 3 Protect Level Setting Conditions
Protection Block (Level)
0 (Whole area unprotected)
1 (Upper 1/4 area protected)
2 (Upper 1/2 area protected)
3 (Whole area protected)
Status Register Bits
BP1
BP0
0
0
0
1
1
0
1
1
Protected Area
None
1800h to 1FFFh
1000h to 1FFFh
0000h to 1FFFh
SRWP (bit7)
Status Register Write Protect Settings
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is “1” and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP pin is high, the status registers are
not protected regardless of the SRWP state. The SRWP setting conditions are shown in “Table 4 SRWP Setting
Conditions.”
Table 4 SRWP Setting Conditions
WP Pin
SRWP
Mode
1
0
Software protected
0
0
(SPM)
1
1
Hardware protected
0
1
(HPM)
Bit4, bit5, and bit6 are reserved bits, and have no significance.
Status Register
Unprotected
Protected
Protected Area
Protected
Protected
Unprotected Area
Unprotected
Unprotected
3. Write Enable (WREN)
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is
the same as for setting status register WEN to “1”, and the state is enabled by inputting the write enable command.
“Figure 7 Write Enable” shows the timing waveforms when the write enable operation is performed. The write enable
command consists only of the first bus cycle, and it is initiated by inputting (06h).
• Write (WRITE)
• Status register write (WRSR)
4. Write Disable (WRDI)
The write disable command sets status register WEN to “0” to prohibit unintentional writing. “Figure 8 Write Disable”
shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by
inputting (04h).
The write disable state (WEN “0”) is exited by setting WEN to “1” using the write enable command (06h).
Figure 7 Write Enable
CS
SCK
SI
Mode3 0 1 2 3 4 5 6 7
Mode0
8CLK
06h
(00000110)
Figure 8 Write Disable
CS
SCK
SI
Mode3
Mode0
01 234 567
8CLK
04h
(00000100)
SO
High Impedance
SO
High Impedance
No.NA1473-10/14