LE25FW808 Datasheet, PDF (10/27 Pages) Sanyo Semicon Device – 8M-bit (1024K×8) Serial Flash Memory with High-Density Read Mode

LE25FW808
3. HD_READ Mode Register Setting
Various operation methods of the HD_READ mode can be set to an internal register in the HD_READ mode command
input at the second bus cycle. The register are eight bits in all, and shows the meaning of each bit in the table 3:
HD_READ mode register table. This register setting is effective until the release from HD_READ mode to the normal
mode. It is not necessary to set it again at each temporary stop of reading in the HD_READ mode.
Table 3: HD_READ Mode Register Table
MSB
REGBL2
REGBL1
REGBL0
REGFCLK1
REGFCLK0
REGCL2
REGCL1
BIT
Name
Function
Set value : Set content
7
REGBL2
6
REGBL1
5
REGBL0
Burst length
[REGBL2, REGBL1, REGBL0]
[0, 0, 0]: continuous
[1, 0, 0]: 4words wrap around
[1, 0, 1]: 8 words wrap around
[1, 1, 0]: 16 words wrap around
[1, 1, 1]: 32 words wrap around
4
REGFCLK1
3
REGFCLK0
Clock frequency
[REGFCLK1, REGFCLK0]
[0, 0]: 16MHz or less + power save mode
[0, 1]: 25MHz or less
[1, 0]: 50MHz or less
[1, 1]: 51MHz or more (1)
2
REGCL2
1
REGCL1
Clock latency
[REGCL2, REGCL1, REGCL0]
[0, 0, 0]: Clock latency = 0.5 (2)
[0, 0, 1]: Clock latency = 1.0
[0, 1, 0]: Clock latency = 1.5
[0, 1, 1]: Clock latency = 2.0
0
REGCL0
[1, 0, 0]: Clock latency = 2.5
[1, 0, 1]: Clock latency = 3.0
(1) The specification that exceeds fCLK=50MHz is planning.
(2) When fCLK exceeds 30MHz, it is necessary to adjust the CL to 1.0 or more.
LSB
REGCL0
Burst length setting
In this model, two kinds of reading methods of "Continuous reading" and "Wrap around reading" in the HD_READ
mode can be set alternately. And, the delimitation of the address can be set to four kinds (every 4 words, 8 words, 16
words, and 32 words (one word =16 bits)) in "Wrap around reading".
• Continuous reading
When the burst length is set, the Continuous reading is set by specifying (0, 0, 0) the register bit.
The Continuous reading method automatically continues to read as long as the SCK is input. Reading is begun from
the input address, and an internal address is automatically count up by two addresses (every 16 bits). If the internal
address reaches to the final address (FFFFEh), it returns to the first address (00000h) and reading is continued. If it
wants to shift to an arbitrary address on the way, the operation that makes CS to H once and makes to L again is
done.
No.A0839-10/27